Phase coupled operation assignment for VLIW processors with distributed register files

International Symposium on System Synthesis (IEEE Cat. No.01EX526) ◽

10.1109/isss.2001.957925 ◽

2002 ◽

Author(s):

M. Bekooij ◽

J. Jess ◽

J. van Meerbergen

Keyword(s):

Vliw Processors ◽

Register Files ◽

Operation Assignment

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Phase coupled operation assignment for VLIW processors with distributed register files

International Symposium on System Synthesis (IEEE Cat. No.01EX526) ◽

10.1145/500001.500029 ◽

2001 ◽

Author(s):

Marco Bekooij ◽

Jochen Jess ◽

Jef van Meerbergen

Keyword(s):

Vliw Processors ◽

Register Files ◽

Operation Assignment

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Branch prediction techniques for low-power VLIW processors

Proceedings of the 13th ACM Great Lakes Symposium on VLSI - GLSVLSI '03 ◽

10.1145/764808.764866 ◽

2003 ◽

Author(s):

G. Palermo ◽

M. Sam ◽

C. Silvan ◽

V. Zaccari ◽

R. Zafalo

Keyword(s):

Low Power ◽

Branch Prediction ◽

Vliw Processors ◽

Prediction Techniques

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A compiler optimization to reduce soft errors in register files

Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems - LCTES '09 ◽

10.1145/1542452.1542459 ◽

2009 ◽

Author(s):

Jongeun Lee ◽

Aviral Shrivastava

Keyword(s):

Compiler Optimization ◽

Soft Errors ◽

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Single-chip multi-processor integrating quadruple 8-way vliw processors with interface timing analysis considering power supply noise

Asia and South Pacific Conference on Design Automation, 2006. ◽

10.1109/aspdac.2006.1594741 ◽

2006 ◽

Author(s):

S. Imai ◽

A. Inoue ◽

M. Matsumura ◽

K. Kawasaki ◽

A. Suga

Keyword(s):

Power Supply ◽

Timing Analysis ◽

Power Supply Noise ◽

Single Chip ◽

Vliw Processors ◽

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Code scheduling for VLIW/superscalar processors with limited register files

ACM SIGMICRO Newsletter ◽

10.1145/144965.145802 ◽

1992 ◽

Vol 23 (1-2) ◽

pp. 197-201

Author(s):

Tokuzo Kiyohara ◽

John C. Gyllenhaal

Keyword(s):

Superscalar Processors ◽

Register Files ◽

Code Scheduling

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An efficient heuristic for instruction scheduling on clustered vliw processors

Proceedings of the 14th international conference on Compilers, architectures and synthesis for embedded systems - CASES '11 ◽

10.1145/2038698.2038707 ◽

2011 ◽

Author(s):

Xuemeng Zhang ◽

Hui Wu ◽

Jingling Xue

Keyword(s):

Instruction Scheduling ◽

Vliw Processors

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Area and Timing Estimation in Register Files Using Neural Networks

Circuits and Systems ◽

10.4236/cs.2012.33037 ◽

2012 ◽

Vol 03 (03) ◽

pp. 269-277

Author(s):

Assim Sagahyroon ◽

Jamal Abdalla

Keyword(s):

Neural Networks ◽

Timing Estimation ◽

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Analysis of Soft Error Mitigation Techniques for Register Files in IBM Cu-08 90nm Technology

2006 49th IEEE International Midwest Symposium on Circuits and Systems ◽

10.1109/mwscas.2006.382112 ◽

2006 ◽

Author(s):

Riaz Naseer ◽

Rashed Zafar Bhatti ◽

Jeff Draper

Keyword(s):

Error Mitigation ◽

Register Files ◽

Mitigation Techniques ◽

Soft Error Mitigation

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Dynamic Capping of Physical Register Files in Simultaneous Multi-threading Processors for Performance

Communications in Computer and Information Science - Computer and Information Sciences ◽

10.1007/978-3-030-00840-6_5 ◽

2018 ◽

pp. 41-48

Author(s):

Hasancan Güngörer ◽

Gürhan Küçük

Keyword(s):

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Making wide-issue VLIW processors viable on FPGAs

ACM Transactions on Architecture and Code Optimization ◽

10.1145/2086696.2086712 ◽

2012 ◽

Vol 8 (4) ◽

pp. 1-16 ◽

Author(s):

Madhura Purnaprajna ◽

Paolo Ienne

Keyword(s):

Vliw Processors ◽

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