Asia and South Pacific Conference on Design Automation, 2006.
Latest Publications

TOTAL DOCUMENTS

375

(FIVE YEARS 0)

H-INDEX

(FIVE YEARS 0)

Published By IEEE

0780394518

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Single-chip multi-processor integrating quadruple 8-way vliw processors with interface timing analysis considering power supply noise

Asia and South Pacific Conference on Design Automation, 2006. ◽

10.1109/aspdac.2006.1594741 ◽

2006 ◽

Author(s):

S. Imai ◽

A. Inoue ◽

M. Matsumura ◽

K. Kawasaki ◽

A. Suga

Keyword(s):

Power Supply ◽

Timing Analysis ◽

Power Supply Noise ◽

Single Chip ◽

Vliw Processors ◽

Supply Noise

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A fast logic simulator using a look up table cascade emulator

Asia and South Pacific Conference on Design Automation, 2006. ◽

10.1109/aspdac.2006.1594729 ◽

2006 ◽

Cited By ~ 1

Author(s):

H. Nakahara ◽

T. Sasao ◽

M. Matsuura

Keyword(s):

Look Up Table

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Newton: a library-based analytical synthesis tool for RF-MEMS resonators

Asia and South Pacific Conference on Design Automation, 2006. ◽

10.1109/aspdac.2006.1594695 ◽

2006 ◽

Author(s):

M.S. McCorquodale ◽

J.L. McCann ◽

R.B. Brown

Keyword(s):

Rf Mems ◽

Mems Resonators ◽

Synthesis Tool ◽

Analytical Synthesis

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A 476-gate-count dynamic optically reconfigurable gate array VLSI chip in a standard 0.35μ CMOS technology

Asia and South Pacific Conference on Design Automation, 2006. ◽

10.1109/aspdac.2006.1594660 ◽

2006 ◽

Cited By ~ 1

Author(s):

M. Watanabe ◽

F. Kobayashi

Keyword(s):

Cmos Technology ◽

Vlsi Chip ◽

Gate Count ◽

Gate Array

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Low-power design methodology for module-wise dynamic voltage and frequency scaling with dynamic de-skewing systems

Asia and South Pacific Conference on Design Automation, 2006. ◽

10.1109/aspdac.2006.1594740 ◽

2006 ◽

Cited By ~ 1

Author(s):

T. Kitahara ◽

H. Hara ◽

S. Shiraiaki ◽

Y. Tsukiboshi ◽

T. Yoda ◽

...

Keyword(s):

Low Power ◽

Design Methodology ◽

Low Power Design ◽

Frequency Scaling ◽

Dynamic Voltage

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Delay defect screening for a 2.16GHz SPARC64 microprocessor

Asia and South Pacific Conference on Design Automation, 2006. ◽

10.1109/aspdac.2006.1594706 ◽

2006 ◽

Cited By ~ 1

Author(s):

N. Ito ◽

A. Kanuma ◽

D. Maruyama ◽

H. Yamanaka ◽

T. Mochizuki ◽

...

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Parlgran: parallelism granularity selection for scheduling task chains on dynamically reconfigurable architectures

Asia and South Pacific Conference on Design Automation, 2006. ◽

10.1109/aspdac.2006.1594733 ◽

2006 ◽

Cited By ~ 2

Author(s):

S. Banerjee ◽

E. Bozorgzadeh ◽

Nikil Dutt

Keyword(s):

Reconfigurable Architectures ◽

Dynamically Reconfigurable ◽

Selection For

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Yield-area optimizations of digital circuits using non-dominated sorting genetic algorithm (yoga)

Asia and South Pacific Conference on Design Automation, 2006. ◽

10.1109/aspdac.2006.1594771 ◽

2006 ◽

Author(s):

V. Agarwal ◽

J. Wang

Keyword(s):

Genetic Algorithm ◽

Digital Circuits

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A real-time and bandwidth guaranteed arbitration algorithm for SoC bus communication

Asia and South Pacific Conference on Design Automation, 2006. ◽

10.1109/aspdac.2006.1594751 ◽

2006 ◽

Cited By ~ 1

Author(s):

Chien-Hua Chen ◽

Geeng-Wei Lee ◽

Juinn-Dar Huang ◽

Jing-Yang Jou

Keyword(s):

Real Time

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Word level functional coverage computation

Asia and South Pacific Conference on Design Automation, 2006. ◽

10.1109/aspdac.2006.1594637 ◽

2006 ◽

Author(s):

B. Alizadeh

Keyword(s):

Word Level ◽

Functional Coverage

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Asia and South Pacific Conference on Design Automation, 2006.Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Single-chip multi-processor integrating quadruple 8-way vliw processors with interface timing analysis considering power supply noise

A fast logic simulator using a look up table cascade emulator

Newton: a library-based analytical synthesis tool for RF-MEMS resonators

A 476-gate-count dynamic optically reconfigurable gate array VLSI chip in a standard 0.35μ CMOS technology

Low-power design methodology for module-wise dynamic voltage and frequency scaling with dynamic de-skewing systems

Delay defect screening for a 2.16GHz SPARC64 microprocessor

Parlgran: parallelism granularity selection for scheduling task chains on dynamically reconfigurable architectures

Yield-area optimizations of digital circuits using non-dominated sorting genetic algorithm (yoga)

A real-time and bandwidth guaranteed arbitration algorithm for SoC bus communication

Word level functional coverage computation

Asia and South Pacific Conference on Design Automation, 2006.
Latest Publications