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TSV Placement and Core Mapping for 3D Mesh Based Network-on-Chip Design Using Extended Kernighan-Lin Partitioning
2015 IEEE Computer Society Annual Symposium on VLSI
◽
10.1109/isvlsi.2015.9
◽
2015
◽
Cited By ~ 4
Author(s):
Kanchan Manna
◽
Vadapalli Shanmukha Sri Teja
◽
Santanu Chattopadhyay
◽
Indranil Sengupta
Keyword(s):
Network On Chip
◽
Chip Design
◽
3D Mesh
◽
On Chip
◽
Core Mapping
Download Full-text
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Rapid Topology Generation and Core Mapping of Optical Network-on-Chip for Heterogeneous Computing Platform
IEEE Access
◽
10.1109/access.2021.3102270
◽
2021
◽
pp. 1-1
Author(s):
Yong Wook Kim
◽
Seo Hong Choi
◽
Tae Hee Han
Keyword(s):
Heterogeneous Computing
◽
Optical Network
◽
Network On Chip
◽
Computing Platform
◽
Topology Generation
◽
On Chip
◽
Core Mapping
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Heterogeneous Computing Platform
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A fault-tolerant network-on-chip design using dynamic reconfiguration of partial-faulty routing resources
2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip
◽
10.1109/vlsisoc.2011.6081674
◽
2011
◽
Author(s):
Zhiliang Qian
◽
Ying Fei Teh
◽
Chi-Ying Tsui
Keyword(s):
Fault Tolerant
◽
Dynamic Reconfiguration
◽
Network On Chip
◽
Chip Design
◽
On Chip
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DIA-TORUS:A Novel Topology for Network on Chip Design
International journal of Computer Networks & Communications
◽
10.5121/ijcnc.2016.8310
◽
2016
◽
Vol 8
(3)
◽
pp. 137-148
Author(s):
Deewakar Thakyal
◽
Pushpita Chatterjee
Keyword(s):
Network On Chip
◽
Chip Design
◽
On Chip
Download Full-text
Network-on-Chip design and synthesis outlook
Integration
◽
10.1016/j.vlsi.2007.12.002
◽
2008
◽
Vol 41
(3)
◽
pp. 340-359
◽
Cited By ~ 79
Author(s):
David Atienza
◽
Federico Angiolini
◽
Srinivasan Murali
◽
Antonio Pullini
◽
Luca Benini
◽
...
Keyword(s):
Network On Chip
◽
Chip Design
◽
Design And Synthesis
◽
On Chip
Download Full-text
On-Chip Processor Traffic Modeling for Network-on-Chip Design
Embedded Multi-Core Systems - Networks-on-Chips
◽
10.1201/9781420079791.ch4
◽
2009
◽
pp. 95-121
Author(s):
Antoine Scherrer
◽
Tanguy Risset
◽
Antoine Fraboulet
Keyword(s):
Network On Chip
◽
Traffic Modeling
◽
Chip Design
◽
On Chip
Download Full-text
Application-specific 3D Network-on-Chip design using simulated allocation
2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)
◽
10.1109/aspdac.2010.5419830
◽
2010
◽
Cited By ~ 4
Author(s):
Pingqiang Zhou
◽
Ping-Hung Yuh
◽
Sachin S. Sapatnekar
Keyword(s):
Network On Chip
◽
Chip Design
◽
3D Network
◽
On Chip
◽
Application Specific
Download Full-text
Timing-Error-Tolerant Network-on-Chip Design Methodology
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
◽
10.1109/tcad.2007.891371
◽
2007
◽
Vol 26
(7)
◽
pp. 1297-1310
◽
Cited By ~ 16
Author(s):
Rutuparna Tamhankar
◽
Srinivasan Murali
◽
Stergios Stergiou
◽
Antonio Pullini
◽
Federico Angiolini
◽
...
Keyword(s):
Design Methodology
◽
Network On Chip
◽
Timing Error
◽
Chip Design
◽
On Chip
Download Full-text
Photonic Network-on-Chip Design
10.1007/978-1-4419-9335-9
◽
2014
◽
Cited By ~ 44
Author(s):
Keren Bergman
◽
Luca P. Carloni
◽
Aleksandr Biberman
◽
Johnnie Chan
◽
Gilbert Hendry
Keyword(s):
Network On Chip
◽
Chip Design
◽
Photonic Network
◽
On Chip
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LPNet: A DNN based latency prediction technique for application mapping in Network-on-Chip design
Microprocessors and Microsystems
◽
10.1016/j.micpro.2021.104370
◽
2021
◽
pp. 104370
Author(s):
Sambangi Ramesh
◽
Manghnani Hitesh
◽
Santanu Chattopadhyay
Keyword(s):
Network On Chip
◽
Chip Design
◽
Application Mapping
◽
Prediction Technique
◽
On Chip
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Multi-application Based Fault-Tolerant Network-on-Chip Design for Mesh Topology Using Reconfigurable Architecture
Communications in Computer and Information Science - VLSI Design and Test
◽
10.1007/978-981-32-9767-8_37
◽
2019
◽
pp. 442-454
Author(s):
P. Veda Bhanu
◽
Pranav V. Kulkarni
◽
Sai Pranavi Avadhanam
◽
J. Soumya
◽
Linga Reddy Cenkeramaddi
Keyword(s):
Fault Tolerant
◽
Network On Chip
◽
Reconfigurable Architecture
◽
Chip Design
◽
Mesh Topology
◽
On Chip
Download Full-text
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