2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip
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Published By IEEE

9781457701702, 9781457701719, 9781457701696

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

A fault-tolerant network-on-chip design using dynamic reconfiguration of partial-faulty routing resources

2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip ◽

10.1109/vlsisoc.2011.6081674 ◽

2011 ◽

Author(s):

Zhiliang Qian ◽

Ying Fei Teh ◽

Chi-Ying Tsui

Keyword(s):

Fault Tolerant ◽

Dynamic Reconfiguration ◽

Network On Chip ◽

Chip Design ◽

On Chip

A fault-tolerant NoC using combined link sharing and partial fault link utilization scheme

2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip ◽

10.1109/vlsisoc.2011.6081595 ◽

2011 ◽

Author(s):

Ying Fei Teh ◽

ZhiLiang Qian ◽

Chi-Ying Tsui

Keyword(s):

Fault Tolerant ◽

Link Utilization ◽

Utilization Scheme

A subthreshold digital maximum power point tracker for micropower piezoelectric energy harvesting applications

2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip ◽

10.1109/vlsisoc.2011.6081610 ◽

2011 ◽

Cited By ~ 1

Author(s):

Joseph Sankman ◽

Dongsheng Ma

Keyword(s):

Energy Harvesting ◽

Maximum Power ◽

Piezoelectric Energy Harvesting ◽

Maximum Power Point ◽

Maximum Power Point Tracker ◽

Piezoelectric Energy ◽

Power Point

Multirate hybrid continuous-time/discrete-time cascade 2–2 ΣΔ modulator for wideband telecom

2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip ◽

10.1109/vlsisoc.2011.6081599 ◽

2011 ◽

Author(s):

J. Gerardo Garcia-Sanchez ◽

Jose M. de la Rosa

Keyword(s):

Discrete Time ◽

Continuous Time

STT-RAM based energy-efficiency hybrid cache for CMPs

2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip ◽

10.1109/vlsisoc.2011.6081626 ◽

2011 ◽

Cited By ~ 46

Author(s):

Jianhua Li ◽

Chun Jason Xue ◽

Yinlong Xu

Keyword(s):

Energy Efficiency ◽

Hybrid Cache

A more efficient arrangement of the sparse LU factorization for the large-scale circuit analysis

2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip ◽

10.1109/vlsisoc.2011.6081619 ◽

2011 ◽

Cited By ~ 1

Author(s):

Josef Dobes ◽

David Cerny ◽

Abhimanyu Yadav

Keyword(s):

Large Scale ◽

Circuit Analysis ◽

Lu Factorization

MCM-based implementation of block FIR filters for high-speed and low-power applications

2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip ◽

10.1109/vlsisoc.2011.6081653 ◽

2011 ◽

Cited By ~ 4

Author(s):

Pramod Kumar Meher ◽

Yu Pan

Keyword(s):

Low Power ◽

High Speed ◽

Fir Filters

3D NoC using through silicon Via: An asynchronous implementation

2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip ◽

10.1109/vlsisoc.2011.6081643 ◽

2011 ◽

Cited By ~ 7

Author(s):

Pascal Vivet ◽

Denis Dutoit ◽

Yvain Thonnart ◽

Fabien Clermidy

Keyword(s):

Through Silicon Via

Frequency-domain transient analysis of multitime partial differential equation systems

2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip ◽

10.1109/vlsisoc.2011.6081663 ◽

2011 ◽

Author(s):

Haotian Liu ◽

Fengrui Shi ◽

Yuanzhe Wang ◽

Ngai Wong

Keyword(s):

Differential Equation ◽

Partial Differential Equation ◽

Frequency Domain ◽

Transient Analysis ◽

Partial Differential

Layout guidelines for 3D architectures including Optical Ring Network-on-Chip (ORNoC)

2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip ◽

10.1109/vlsisoc.2011.6081645 ◽

2011 ◽

Cited By ~ 10

Author(s):

Sebastien Le Beux ◽

Jelena Trajkovic ◽

Ian O'Connor ◽

Gabriela Nicolescu

Keyword(s):

Network On Chip ◽

Ring Network ◽

On Chip ◽

Optical Ring

2011 IEEE/IFIP 19th International Conference on VLSI and System-on-ChipLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

A fault-tolerant network-on-chip design using dynamic reconfiguration of partial-faulty routing resources

A fault-tolerant NoC using combined link sharing and partial fault link utilization scheme

A subthreshold digital maximum power point tracker for micropower piezoelectric energy harvesting applications

Multirate hybrid continuous-time/discrete-time cascade 2–2 ΣΔ modulator for wideband telecom

STT-RAM based energy-efficiency hybrid cache for CMPs

A more efficient arrangement of the sparse LU factorization for the large-scale circuit analysis

MCM-based implementation of block FIR filters for high-speed and low-power applications

3D NoC using through silicon Via: An asynchronous implementation

Frequency-domain transient analysis of multitime partial differential equation systems

Layout guidelines for 3D architectures including Optical Ring Network-on-Chip (ORNoC)

2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip
Latest Publications