Scalable Resonant Power Clock Generation for Adiabatic Logic Design

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Keyword(s):  
Logic Design ◽  
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Adiabatic Logic

Evolutionary Approach of Adiabatic Logic Design on Low Power Solution �A Robust Survey

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scholarly journals Low Power Adiabatic Logic Design

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Adiabatic Logic

scholarly journals Modelling, simulation and verification of 4-phase adiabatic logic design: A VHDL-Based approach

Integration ◽  
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Vol 67 ◽  
pp. 144-154 ◽  
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V.A. Bartlett ◽  
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scholarly journals Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality

2005 ◽  
Author(s):  
M. Beck ◽  
O. Barondeau ◽  
M. Kaibel ◽  
F. Poehl ◽  
Xijiang Lin ◽  
...  
Keyword(s):  
Logic Design ◽  
Delay Test ◽  
Test Quality ◽  
Clock Generation ◽  
On Chip
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