Area and Energy Efficient QCA Based Compact Serial Concatenated Convolutional Code Encoder

Quantum-dot Cellular Automata (QCA) is a transistor-less technology known for its low power consumption and higher clock rate. Serial Concatenated Convolutional Coding (SCCC) encoder is a class of forward error correction. This paper picturizes the implementation of the outer encoder as a (7, 4, 1) Bose Chaudhary Hocquenghem encoder that serves the purpose of burst error correction, a pseudo-random inter-leaver used for permuting of systematic code words and finally the inner encoder which is used for the correction of random errors in QCA. Two different architectures of the SCCC encoder have been proposed and discussed in this study. In the proposed two architectures, the first based on external clock signals whereas the second based on internal clock generation. The sub-blocks outer encoder, pseudo-random inter-leaver and inner encoder of the SCCC encoder are optimized, implemented and simulated using QCADesigner and then integrated to design a compact SCCC encoder. The energy dissipation is computed using QCADesigner-E. The proposed SCCC encoder reduced the total area by 46% and energy dissipation by 50% when compared to the reference SCCC encoder. The proposed encoders are more efficient in terms of cell count, energy dissipation and area occupancy respectively.

Software architecture for display controller and operating system interaction

Article describes solutions for developing programs that provide interaction between Linux operating system and multiple display controller hardware blocks (outputs), that use one clock generation IP-block with phase-locked loop (PLL). There is no API for such devices in Linux, thus new software model was developed. This model is based on official Linux GPU developer driver model, but was modified to cover case described earlier. Article describes three models for display controller driver development – monolithic, component and semi-monolithic. These models cannot cover case described earlier, because they assume that one clock generator should be attached to one output. A new model was developed, that is based on component model, but has additional mechanics to prevent race condition that can happen while using one clock generator with multiple outputs. Article also presents modified model for bootloaders graphics drivers. This model has been simplified over developed Linux model, but also has component nature (with less components) and race prevention mechanics (but with weaker conditions). Hardware interaction driver components that are developed using provided software models are interchangeable between Linux and bootloader.

Variable Clock and EM Signal Generation Scheme for Foveation-Based Driving OLED Head-Mounted Displays

An image processing pipeline and multi-output shift register of a foveation-based driving scheme are proposed for the realization of immersive head-mounted displays in 2019. In addition, this paper describes a variable clock generation circuit to manipulate output waveforms of shift registers in the foveated display. The EM circuit for OLED displays is also introduced to support the control signal to keep OLEDs of pixels from emitting light during the compensation. Especially, the EM circuit consists of only four TFTs and one capacitor and gives rise to pulses of variable widths corresponding to the resolution of a driven display area. A variable clock generation scheme is verified with 60 Hz 1440 × 2560 monitor, eye-tracker, PSoC board and FPGA board. An EM circuit is simulated by SPICE for 9600 lines and 120 Hz foveated displays.

Digitally Controlled Oscillator with High Timing Resolution and Low Complexity for Clock Generation

This paper presents a digitally controlled oscillator (DCO) with a low-complexity circuit structure that combines multiple delay circuits to achieve a high timing resolution and wide output frequency range simultaneously while also significantly reducing the overall power consumption. A 0.18 µm complementary metal–oxide–semiconductor standard process was used for the design, and measurements showed that the chip had a minimum controllable timing resolution of 4.81 ps and power consumption of 142 µW with an output signal of 364 MHz. When compared with other designs using advanced processes, the proposed DCO demonstrated the best power-to-frequency ratio. Therefore, it can output a signal at the required frequency more efficiently in terms of power consumption. Additionally, because the proposed DCO uses digital logic gates only, a cell-based design flow can be implemented. Hence, the proposed DCO is not only easy to implement in different processes but also easy to integrate with other digital circuits.

The Demonstration of S2P (Serial-to-Parallel) Converter with Address Allocation Method Using 28 nm CMOS Technology

To improve the performance of analog, RF, and digital integrated circuits, the cutting-edge advanced CMOS technology has been widely utilized. We successfully designed and implemented a high-speed and low-power serial-to-parallel (S2P) converter for 5G applications based on the 28 nm CMOS technology. It can update data easily and quickly using the proposed address allocation method. To verify the performances, an embedded system (NI-FPGA) for fast clock generation on the evaluation board level was also used. The proposed S2P converter circuit shows extremely low power consumption of 28.1 uW at 0.91 V with a core die area of 60 × 60 μm2 and operates successfully over a wide clock frequency range from 5 M to 40 MHz.