A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Self-Biased PLL-Based Multiphase Clock Generator

2020 ◽  
Vol 55 (10) ◽  
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Guang Zhu ◽  
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Li Wang ◽  
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2009 ◽  
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pp. 6-10 ◽  
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...  


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1985 ◽  
Vol 21 (22) ◽  
pp. 1012 ◽  
Author(s):  
K. Holejko ◽  
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Vol 42 (3-4) ◽  
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Atheer Barghouthi ◽  
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Author(s):  
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A. Barghouthi ◽  
C. Knochenhauer ◽  
F. Ellinger ◽  
C. Scheytt


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