A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Self-Biased PLL-Based Multiphase Clock Generator
2020 ◽
Vol 55
(10)
◽
pp. 2734-2746
2009 ◽
Vol 56
(1)
◽
pp. 6-10
◽
Keyword(s):
Keyword(s):
1987 ◽
Vol 42
(3-4)
◽
pp. 132-134