A 32-Gb/s 0.46-pJ/bit PAM4 CDR Using a Quarter-Rate Linear Phase Detector and a Self-Biased PLL-Based Multiphase Clock Generator

2020 ◽  
Vol 55 (10) ◽  
pp. 2734-2746
Author(s):  
Zhao Zhang ◽  
Guang Zhu ◽  
Can Wang ◽  
Li Wang ◽  
C. Patrick Yue
2009 ◽  
Vol 56 (1) ◽  
pp. 6-10 ◽  
Author(s):  
Young-Suk Seo ◽  
Jang-Woo Lee ◽  
Hong-Jung Kim ◽  
Changsik Yoo ◽  
Jae-Jin Lee ◽  
...  

Author(s):  
Chorng-Sii Hwang ◽  
Chun-Yung Cho ◽  
Chung-Chun Chen ◽  
Hen-Wai Tsao

Author(s):  
Niko Joram ◽  
Atheer Barghouthi ◽  
Christian Knochenhauer ◽  
Frank Ellinger ◽  
Christoph Scheytt

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