Adaptive Data-Transition Decision Feedback Equalizers For High-Speed Serial Links

This dissertation investigates adaptive decision feedback equalizers for high-speed serial data links.<div>An adaptive data-transition decision feedback equalizer (DT-DFE) was developed. The DT-DFE boosts the eye-opening of the high-frequency components of data without attenuating their low-frequency counterparts. Reference voltages were obtained by transmitting consecutive 1s and 0s and measuring the output of the continuous-time linear equalizer using a pair of successive approximation register analog-to-digital converters in a training phase. It uses loop unrolling to detect data transitions, activate tap-tuning, launch DFE, and combat timing constraints. The performance of the DT-DFE and its advantages over commonly used data-state DFE were validated using the schematic-level simulation results of 5 Gbps backplane links.<br></div><div>A new adaptive DT-DFE with edge-emphasis (EE) taps and raised references was developed. Loop-unrolling was further developed for DT-DFE with EE-taps. The reference voltages were raised beyond that set by the low-frequency components of data to increase vertical eye-opening. Clock and data recovery was performed using 4x oversampling. The DT-DFE was validated using the schematiclevel simulation results of 10 Gbps backplane links.<br></div><div>A pre-skewed bi-directional gated delay line (BDGDL) bang-bang frequency difference-to-digital converter and a BDGDL integrating frequency difference-todigital converter (iFDDC) were proposed for clock and data recovery. Both frequency difference detectors feature all-digital realization, low power consumption, and high-speed operation. The built-in integration of iFDDC results in a zero static frequency error and the first-order noise-shaping of the quantization errors of the BDGDL and digitally-controlled oscillators. Their effectiveness was validated using schematic-level simulation results of 5-GHz frequency-locked loops.<br></div><div>All systems validating the proposed adaptive DFE and frequency-difference detectors were designed in TSMC’s 65 nm CMOS technology and analyzed using Spectre from Cadence Design Systems. <br></div>

Adaptive Data-Transition Decision Feedback Equalizers For High-Speed Serial Links

This dissertation investigates adaptive decision feedback equalizers for high-speed serial data links.<div>An adaptive data-transition decision feedback equalizer (DT-DFE) was developed. The DT-DFE boosts the eye-opening of the high-frequency components of data without attenuating their low-frequency counterparts. Reference voltages were obtained by transmitting consecutive 1s and 0s and measuring the output of the continuous-time linear equalizer using a pair of successive approximation register analog-to-digital converters in a training phase. It uses loop unrolling to detect data transitions, activate tap-tuning, launch DFE, and combat timing constraints. The performance of the DT-DFE and its advantages over commonly used data-state DFE were validated using the schematic-level simulation results of 5 Gbps backplane links.<br></div><div>A new adaptive DT-DFE with edge-emphasis (EE) taps and raised references was developed. Loop-unrolling was further developed for DT-DFE with EE-taps. The reference voltages were raised beyond that set by the low-frequency components of data to increase vertical eye-opening. Clock and data recovery was performed using 4x oversampling. The DT-DFE was validated using the schematiclevel simulation results of 10 Gbps backplane links.<br></div><div>A pre-skewed bi-directional gated delay line (BDGDL) bang-bang frequency difference-to-digital converter and a BDGDL integrating frequency difference-todigital converter (iFDDC) were proposed for clock and data recovery. Both frequency difference detectors feature all-digital realization, low power consumption, and high-speed operation. The built-in integration of iFDDC results in a zero static frequency error and the first-order noise-shaping of the quantization errors of the BDGDL and digitally-controlled oscillators. Their effectiveness was validated using schematic-level simulation results of 5-GHz frequency-locked loops.<br></div><div>All systems validating the proposed adaptive DFE and frequency-difference detectors were designed in TSMC’s 65 nm CMOS technology and analyzed using Spectre from Cadence Design Systems. <br></div>

Cloud Computing Storage Backup and Recovery Strategy Based on Secure IoT and Spark

Spatial data occupies a large proportion of the large amount of data that is constantly emerging, but a large amount of spatial data cannot be directly understood by people. Even a highly configured stand-alone computing device can hardly meet the needs of visualization processing. In order to protect the security of data and facilitate for users the search for data and recover by mistake, this paper conducts a research on cloud computing storage backup and recovery strategies based on the secure Internet of Things and Spark platform. In the method part, this article introduces the security Internet of Things, Spark, and cloud computing backup and recovery related content and proposes cluster analysis and Ullman two algorithms. In the experimental part, this article explains the experimental environment and experimental objects and designs an experiment for data recovery. In the analysis part, this article analyzes the challenge-response-verification framework, the number of data packets, the cost of calculation and communication, the choice of Spark method, the throughput of different platforms, and the iteration and cache analysis. The experimental results show that the loss rate of database 1 in the fourth node is 0.4%, 2.4%, 1.6%, and 3.2% and the loss rate of each node is less than 5%, indicating that the system can respond to applications.

Multi-Timescale Load Forecast of Large Power Customers Based on Online Data Recovery and Time Series Neural Networks

This paper presents a multi-timescale receding horizon framework for the load forecast of large power customers. The future load pattern of individual users could be very difficult to predict because of its chronological and high volatile properties. Also, the sampling of nonaggregated load data may suffer from severe information missing issues. To address these challenges, we first develop an online singular value thresholding (SVT) algorithm, which utilizes the approximate low-rank property of load data matrices to efficiently recover the missing information. Then, a combinatorial deep learning method is developed, which applies the multi-layer perception (MLP) neural network and the long short-term memory (LSTM) neural network with gated recurrent unit (GRU) to deal with the short-term and ultra-short-term load forecast, respectively. Specifically, an early stopping strategy is designed and implemented to avoid the over-fitting of model training. Moreover, the receding time window is imposed to dynamically update the data recovery and load forecast outcomes, which supports the online computing on a Spark platform. Numerical experiments on real-world load data from North China confirms the effectiveness of the proposed methodology, which can support more complex applications in embedded systems and cyber physical systems.