Design of Bandwidth Aware and Congestion Avoiding Efficient Routing Algorithms for Networks-on-Chip Platforms

2008 ◽  
Author(s):  
Maurizio Palesi ◽  
Giuseppe Longo ◽  
Salvatore Signorino ◽  
Rickard Holsmark ◽  
Shashi Kumar ◽  
...  
Keyword(s):  
Routing Algorithms ◽  
Networks On Chip ◽  
On Chip

scholarly journals Networks-On-Chip Based on Dynamic Wormhole Packet Identity Mapping Management

VLSI Design ◽  
2009 ◽  
Vol 2009 ◽  
pp. 1-15 ◽  
Author(s):  
Faizal A. Samman ◽  
Thomas Hollstein ◽  
Manfred Glesner
Keyword(s):  
Identity Management ◽  
Routing Algorithms ◽  
Communication Link ◽  
Message Delivery ◽  
Networks On Chip ◽  
Design Flexibility ◽  
Parallel Pipeline ◽  
On Chip ◽  
Switching Method ◽  
Flexible Infrastructure

This paper presents a network-on-chip (NoC) with flexible infrastructure based on dynamic wormhole packet identity management. The NoCs are developed based on a VHDL approach and support the design flexibility. The on-chip router uses a wormhole packet switching method with a synchronous parallel pipeline technique. Routing algorithms and dynamic wormhole local packet identity (ID-tag) mapping management are proposed to support a wire sharing methodology and an ID slot division multiplexing technique. At each communication link, flits belonging to the same message have the same local ID-tag, and the ID-tag is updated before the packet enters the next communication link by using an ID-tag mapping management unit. Therefore, flits from different messages can be interleaved, identified, and routed according to their allocated ID slots. Our NoC guarantees in order and lossless message delivery.

Double Stairs: A Fault-Tolerant Routing Algorithm for Networks-on-Chip

2016 ◽  
Vol 25 (06) ◽  
pp. 1650065 ◽  
Author(s):  
Saleh Fakhrali ◽  
Hamid R. Zarandi
Keyword(s):  
Fault Tolerance ◽  
Fault Tolerant ◽  
Routing Algorithm ◽  
Deep Submicron ◽  
Routing Algorithms ◽  
Experimental Results ◽  
Trade Off ◽  
Networks On Chip ◽  
On Chip ◽  
Probabilistic Flooding

Reliability is one of the main concerns in the design of networks-on-chip (NoCs) due to the use of deep submicron technologies in fabrication of such products. This paper presents a new fault-tolerant routing algorithm called double stairs for NoCs. Double stairs routing algorithm is a low overhead routing that has the ability to deal with fault. The proposed routing algorithm makes a redundant copy of each packet at the source node and routes the original and redundant packets in a new partially adaptive routing algorithm. The method is evaluated for various packet injection rates and fault rates. Experimental results show that the proposed routing algorithm offers the best trade-off between performance and fault tolerance compared to other routing algorithms, namely flooding, XYX and probabilistic flooding.

Fault-Tolerant Routing Algorithms in Networks On-Chip

2013 ◽  
pp. 193-210 ◽  
Author(s):  
Reyhaneh Jabbarvand Behrouz ◽  
Mehdi Modarressi ◽  
Hamid Sarbazi-Azad
Keyword(s):  
Fault Tolerant ◽  
Routing Algorithms ◽  
Networks On Chip ◽  
On Chip

scholarly journals ParRouting: An Efficient Area Partition-Based Congestion-Aware Routing Algorithm for NoCs

Micromachines ◽  
2020 ◽  
Vol 11 (12) ◽  
pp. 1034
Author(s):  
Juan Fang ◽  
Di Zhang ◽  
Xiaqing Li
Keyword(s):  
Routing Algorithm ◽  
Central Area ◽  
Routing Algorithms ◽  
Output Node ◽  
Networks On Chip ◽  
Traffic Pattern ◽  
Key Factor ◽  
Congestion Awareness ◽  
On Chip ◽  
Congestion Aware

Routing algorithms is a key factor that determines the performance of NoC (Networks-on-Chip) systems. Regional congestion awareness routing algorithms have shown great potential in improving the performance of NoC. However, it incurs a significant queuing latency when practitioners use existing regional congestion awareness routing algorithms to make routing decisions, thus degrading the performance of NoC. In this paper, we propose an efficient area partition-based congestion-aware routing algorithm, ParRouting, which aims at increasing the throughput and reducing the latency for NoC systems. First, ParRouting partitions the network into two areas (i.e., edge area and central area.) based on node priorities. Then, for the edge area, ParRouting selects the output node based on different priorities for higher throughput; for the central area, ParRouting selects the node in the low congestion direction as the output node for lower queuing latency. Our experimental results indicate that ParRouting achieves a 53.4% reduction in packet average latency over SPLASH -2 ocean application and improves the saturated throughput by up to 38.81% over a synthetic traffic pattern for an NoC system, compared to existing routing algorithms.

Sign in / Sign up

Export Citation Format

Share Document