A review paper on memory fault models and test algorithms

Testing embedded memories in a chip can be very challenging due to their high-density nature and manufactured using very deep submicron (VDSM) technologies. In this review paper, functional fault models which may exist in the memory are described, in terms of their definition and detection requirement. Several memory testing algorithms that are used in memory built-in self-test (BIST) are discussed, in terms of test operation sequences, fault detection ability, and also test complexity. From the studies, it shows that tests with 22 N of complexity such as March SS and March AB are needed to detect all static unlinked or simple faults within the memory cells. The N in the algorithm complexity refers to Nx*Ny*Nz whereby Nx represents the number of rows, Ny represents the number of columns and Nz represents the number of banks. This paper also looks into optimization and further improvement that can be achieved on existing March test algorithms to increase the fault coverage or to reduce the test complexity.

Comparative Study of Hybrid Optimizations Technique for On-Chip Interconnect in Multimedia SoCs

This paper presents the design and analysis of on-chip interconnect architectures for real time Multimedia Systems-on-Chip (MSoC) targeting Internet of Things (IoT) applications. The interconnect architecture provides high flexibility in connection for hardware implementation of reconfigurable neural network. Due to technology’s miniaturization in ultra-deep submicron technology, the on-chip interconnect performance and power consumption become a bottle-neck. In this paper, the hybrid optimization technique is proposed to address these challenges using schmitt trigger as a repeater and tapering. Here, the proposed optimization technique is incorporated with a dedicated point to point based interconnection (PTP-BI) configuration. A comparative study with others without optimization technique (Model–I) shows the effectiveness of the proposed optimization technique (Model–II). The technology node scaling impacts are also analyzed for both techniques. Finally, the percentage reduction of latency and power consumption are evaluated in two different cases to observe the impacts of varying the interconnect length.

A Proposed Technique to Improve the Performance of Receiver by Using Linear Gm-C Low-Pass Filter for mmwave Band Applications

Deep submicron CMOS technology proves to be suitable for transceiver design at mmwave band frequencies. At the same time, it has been a challenging task to obtain high performance at mmwave frequencies. In this paper, a 28[Formula: see text]GHz low-IF receiver frontend with improved performance by incorporating a proposed linear Gm-C low-pass filter (LPF) is presented using 40[Formula: see text]nm CMOS technology targeting for 5G wireless system. A mathematical expression for the linearity of the proposed filter is derived and compared with the basic filter model. The improved linearity (IIP3 of [Formula: see text][Formula: see text]dBm) of the proposed filter results in the enhancement of linearity and hence the Figure of Merit (FOM) of the receiver with the proposed filter. The receiver attains a conversion gain of 34.6[Formula: see text]dB, a noise figure of 3.1[Formula: see text]dB and IIP3 of [Formula: see text][Formula: see text]dBm. The total current drawn by the receiver is 27.3[Formula: see text]mA at a 1.2[Formula: see text]V power supply. The overall FOM of the receiver with the proposed filter is improved to 0.30 whereas the FOM of the receiver with the basic filter model is 0.13. The area of the receiver is [Formula: see text] whereas the proposed filter occupies [Formula: see text].

Fabrication Process for Deep Submicron SQUID Circuits with Three Independent Niobium Layers

We present a fabrication technology for nanoscale superconducting quantum interference devices (SQUIDs) with overdamped superconductor-normal metal-superconductor (SNS) trilayer Nb/HfTi/Nb Josephson junctions. A combination of electron-beam lithography with chemical-mechanical polishing and magnetron sputtering on thermally oxidized Si wafers is used to produce direct current SQUIDs with 100-nm-lateral dimensions for Nb lines and junctions. We extended the process from originally two to three independent Nb layers. This extension offers the possibility to realize superconducting vias to all Nb layers without the HfTi barrier, and hence to increase the density and complexity of circuit structures. We present results on the yield of this process and measurements of SQUID characteristics.

In-SEM micro-machining reveals the origins of the size effect in the cutting energy

High-precision metal cutting is increasingly relevant in advanced applications. Such precision normally requires a cutting feed in the micron or even sub-micron dimension scale, which raises questions about applicability of concepts developed in industrial scale machining. To address this challenge, we have developed a device to perform linear cutting with force measurement in the vacuum chamber of an electron microscope, which has been utilised to study the cutting process down to 200 nm of the feed and the tool tip radius. The machining experiments carried out in-operando in SEM have shown that the main classical deformation zones of metal cutting: primary, secondary and tertiary shear zones—were preserved even at sub-micron feeds. In-operando observations and subsequent structural analysis in FIB/SEM revealed a number of microstructural peculiarities, such as: a substantial increase of the cutting force related to the development of the primary shear zone; dependence of the ternary shear zone thickness on the underlaying grain crystal orientation. Measurement of the cutting forces at deep submicron feeds and cutting tool apex radii has been exploited to discriminate different sources for the size effect on the cutting energy (dependence of the energy on the feed and tool radius). It was observed that typical industrial values of feed and tool radius imposes a size effect determined primarily by geometrical factors, while in a sub-micrometre feed range the contribution of the strain hardening in the primary share zone becomes relevant.