Most digit-recurrence algorithms for division, such as the Sweeney–Robertson–Tocher (SRT) algorithm, have been used in order to take advantage of the redundant representations of the partial remainder. This way, full carry propagate additions are avoided, obtaining significant latency improvements. Furthermore, the delay corresponding to one division iteration is independent of the size of the operands. The most frequent redundant form for the partial remainders is the carry-save (CS) representation, which uses 2 bits of representation (carry and sum bits) for each bit of the partial remainder. This paper proposes radix-4 SRT dividers which use (3, 2) redundancy (3 bits of representation for 2 bits of the partial remainder) and (5, 4) redundancy (5 bits of representation for 4 bits of the partial remainder). The goal of using these representations is represented by a decreased cost due to the reduced number of sequential elements required to store the partial remainder. The proposed dividers use 2-bit carry propagate adders and 4-bit carry propagate adders to compute the new partial remainder. Thus, the full carry propagate addition is avoided, while the latency of one division iteration is independent of the operands’ size. The synthesis result for Xilinx Virtex-5 FPGA devices show that similar working frequencies are obtained for divider using the proposed redundant representation with respect to the conventional carry-save, while requiring up to 12% for (3, 2) representation and 18% for (5, 4) representation less sequential elements.
Low-latency Montgomery AB2 Multiplier Using Redundant Representation Over GF(2m))
