Analyzing Worst-case Delay-Buffer-Equation for wormhole networks on chip

2014 NORCHIP ◽  
2014 ◽  
Author(s):  
Yue Qian ◽  
Junhui Wang
2013 ◽  
Vol 21 (10) ◽  
pp. 1823-1836 ◽  
Author(s):  
Yiyuan Xie ◽  
Mahdi Nikdast ◽  
Jiang Xu ◽  
Xiaowen Wu ◽  
Wei Zhang ◽  
...  

2019 ◽  
Vol 8 (2) ◽  
pp. 414-421 ◽  
Author(s):  
M. Norazizi Sham Mohd Sayuti ◽  
Farida Hazwani Mohd Ridzuan ◽  
Zul Hilmi Abdullah

Interference from high priority tasks and messages in a hard real-time Networks-on-Chip (NoC) create computation and communication delays. As the delays increase in number, maintaining the system’s schedulability become difficult. In order to overcome the problem, one way is to reduce interference in the NoC by changing task mapping and network routing. Some population-based heuristics evaluate the worst-case response times of tasks and messages based on the schedulability analysis, but requires a significant amount of optimization time to complete due to the complexity of the evaluation function. In this paper, we propose an optimization technique that explore both parameters simultaneously with the aim to meet the schedulability of the system, hence reducing the optimization time. One of the advantages from our approach is the unrepeated call to the evaluation function, which is unaddressed in the heuristics that configure design parameters in stages. The results show that a schedulable configuration can be found from the large design space.


2021 ◽  
Author(s):  
Victor. Dumitriu

The Network-on-Chip concept is emerging as a promising new method of addressing the communication requirements of complex Systems-on-Chip. However, network design at this level must take into consideration the specific communication protocols of on-chip components. This thesis presents a topology analysis and design method for networks-on-chip based on the transaction-oriented protocols common to on-chip systems. The generated topologies target the latency of critical links in the system, while the analysis method can predict the degree of contention in a system prior to the simulation phase. The proposed topologies are tested using various applications, including and MPEG4 Decoder, and are found to perform the same or better than regular topologies, while using less network resources. The contention prediction method is found to be accurate to within 27% in the worst case scenario.


2008 ◽  
Vol 13 (1) ◽  
pp. 1-22 ◽  
Author(s):  
Sami Taktak ◽  
Jean-Lou Desbarbieux ◽  
Emmanuelle Encrenaz

2014 ◽  
Vol 60 (6) ◽  
pp. 494-508 ◽  
Author(s):  
Junhui Wang ◽  
Yue Qian ◽  
Yi Wang ◽  
Zili Shao ◽  
Wenhua Dou ◽  
...  
Keyword(s):  

2021 ◽  
Author(s):  
Victor. Dumitriu

The Network-on-Chip concept is emerging as a promising new method of addressing the communication requirements of complex Systems-on-Chip. However, network design at this level must take into consideration the specific communication protocols of on-chip components. This thesis presents a topology analysis and design method for networks-on-chip based on the transaction-oriented protocols common to on-chip systems. The generated topologies target the latency of critical links in the system, while the analysis method can predict the degree of contention in a system prior to the simulation phase. The proposed topologies are tested using various applications, including and MPEG4 Decoder, and are found to perform the same or better than regular topologies, while using less network resources. The contention prediction method is found to be accurate to within 27% in the worst case scenario.


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