Near-Memory Address Translation

2017 26th International Conference on Parallel Architectures and Compilation Techniques (PACT) ◽

10.1109/pact.2017.56 ◽

2017 ◽

Author(s):

Javier Picorel ◽

Djordje Jevdjic ◽

Babak Falsafi

Keyword(s):

Memory Address ◽

Address Translation

Download Full-text

A hardware evaluation of memory address translation for mobile virtualization

2014 International Conference on Information Science, Electronics and Electrical Engineering ◽

10.1109/infoseee.2014.6947817 ◽

2014 ◽

Author(s):

Yuan-Cheng Lee ◽

Chih-Wen Hsueh

Keyword(s):

Memory Address ◽

Address Translation

Download Full-text

A Space-Efficient Caching Mechanism for Flash-Memory Address Translation

Ninth IEEE International Symposium on Object and Component-Oriented Real-Time Distributed Computing (ISORC'06) ◽

10.1109/isorc.2006.13 ◽

2006 ◽

Author(s):

Chin-Hsien Wu ◽

Tei-Wei Kuo ◽

Chia-Lin Yang

Keyword(s):

Flash Memory ◽

Memory Address ◽

Address Translation ◽

Caching Mechanism

Download Full-text

TLB for Free: In-Cache Address Translation for a Multiprocessor Workstation

10.21236/ada611687 ◽

1985 ◽

Author(s):

Scott A. Ritchie

Keyword(s):

Address Translation

Download Full-text

Network Address Translation (NAT)

ACM SIGCOMM Computer Communication Review ◽

10.1145/2766330.2766340 ◽

2015 ◽

Vol 45 (2) ◽

pp. 50-50 ◽

Author(s):

Paul Francis

Keyword(s):

Network Address Translation ◽

Address Translation

Download Full-text

Architectural support for address translation on GPUs

ACM SIGPLAN Notices ◽

10.1145/2644865.2541942 ◽

2014 ◽

Vol 49 (4) ◽

pp. 743-758 ◽

Author(s):

Bharath Pichai ◽

Lisa Hsu ◽

Abhishek Bhattacharjee

Keyword(s):

Architectural Support ◽

Address Translation

Download Full-text

Architectural support for address translation on GPUs

ACM SIGARCH Computer Architecture News ◽

10.1145/2654822.2541942 ◽

2014 ◽

Vol 42 (1) ◽

pp. 743-758 ◽

Author(s):

Bharath Pichai ◽

Lisa Hsu ◽

Abhishek Bhattacharjee

Keyword(s):

Architectural Support ◽

Address Translation

Download Full-text

CARAT: a case for virtual memory through compiler- and runtime-based address translation

Proceedings of the 41st ACM SIGPLAN Conference on Programming Language Design and Implementation ◽

10.1145/3385412.3385987 ◽

2020 ◽

Author(s):

Brian Suchy ◽

Simone Campanoni ◽

Nikos Hardavellas ◽

Peter Dinda

Keyword(s):

Virtual Memory ◽

Address Translation

Download Full-text

Reduced March iC- Test for Detecting Ageing Induced Faults in Memory Address Decoders

2021 34th International Conference on VLSI Design and 2021 20th International Conference on Embedded Systems (VLSID) ◽

10.1109/vlsid51830.2021.00038 ◽

2021 ◽

Author(s):

Kumari Anjali ◽

Shubham Saha ◽

Anuj Grover

Keyword(s):

Memory Address ◽

Address Decoders ◽

Download Full-text

Address translation in telecommunication features

ACM Transactions on Software Engineering and Methodology ◽

10.1145/1005561.1005562 ◽

2004 ◽

Vol 13 (1) ◽

pp. 1-36 ◽

Author(s):

Pamela Zave

Keyword(s):

Address Translation

Download Full-text

Early resolution of address translation in cache design

Proceedings., 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors ◽

10.1109/iccd.1990.130264 ◽

2002 ◽

Author(s):

K. Hua ◽

A. Hunt ◽

L. Liu ◽

J.-K. Peir ◽

D. Pruett ◽

...

Keyword(s):

Address Translation ◽

Download Full-text