address decoders
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Author(s):  
Jack Ou ◽  
Brendon Palmer ◽  
Laurence Hou ◽  
Pietro M. Ferreira
Keyword(s):  

2014 ◽  
Vol 573 ◽  
pp. 169-175
Author(s):  
P. Karthikeyan ◽  
R. Saravanan ◽  
N. Saravanan

In this work low leakage and high noise immunity domino circuit with negligible speed degradation is proposed. Wide Fan-In Gates are widely used as address decoders in memories. Wide Fan-In Gates increase the capacitance of the dynamic node which reduces the speed in domino circuits. Current contention exists between keeper transistor and evaluation network adding to speed reduction. To overcome this problem logic implementation network in the proposed Leakage Compensating Keeper (LCK) is separated from the dynamic node by current comparison stage in which the current of the pull up network is used to charge the capacitor at the dynamic node. Since capacitance is reduced the loss in speed due to additional transistors is compensated. Because of reduced parasitic capacitance Current Mirror based LCK is enough to design faster circuits. LCK improves the noise immunity by grounding the pull up networks leakage current. Simulation results shows that the proposed circuit has 22% power reduction compared to Standard Footless Domino for a 64bit input OR gate.


VLSI Design ◽  
2010 ◽  
Vol 2010 ◽  
pp. 1-7 ◽  
Author(s):  
Sergio Saponara ◽  
Tommaso Baldetti ◽  
Luca Fanucci

The design of a 10-bit resistor-string digital-to-analog converter (DAC) for MOEMS micromirror interfacing is addressed in this paper. The proposed DAC, realized in a 0.18-μm BCD technology, features a folded resistor-string stage with a switch matrix and address decoders plus an output voltage buffer stage. The proposed DAC and buffer circuitry are key elements of an innovative scanning micromirror actuator, characterized by direct digital input, full differential driving, and linear response. With respect to the the state-of-the-art resistor-string converters in similar technologies, the proposed DAC has comparable nonlinearity (INL, DNL) performances while it has the advantage of a smaller area occupation, 0.17 mm2, including output buffer, and relatively low-power consumption, 200 μW at 500 kSPS and few μW in idle mode.


2009 ◽  
Vol 40 (11) ◽  
pp. 1590-1600 ◽  
Author(s):  
Michael A. Turi ◽  
José G. Delgado-Frias

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