Accessible formal verification for safety-critical hardware design

Author(s):  
J. Lach ◽  
S. Bingham ◽  
C. Elks ◽  
T. Lenhart ◽  
Thuy Nguyen ◽  
...  
2015 ◽  
Vol 2015 ◽  
pp. 1-10 ◽  
Author(s):  
Sana Shuja ◽  
Sudarshan K. Srinivasan ◽  
Shaista Jabeen ◽  
Dharmakeerthi Nawarathna

Pacemakers are safety-critical devices whose faulty behaviors can cause harm or even death. Often these faulty behaviors are caused due to bugs in programs used for digital control of pacemakers. We present a formal verification methodology that can be used to check the correctness of object code programs that implement the safety-critical control functions of DDD mode pacemakers. Our methodology is based on the theory of Well-Founded Equivalence Bisimulation (WEB) refinement, where both formal specifications and implementation are treated as transition systems. We develop a simple and general formal specification for DDD mode pacemakers. We also develop correctness proof obligations that can be applied to validate object code programs used for pacemaker control. Using our methodology, we were able to verify a control program with millions of transitions against the simple specification with only 10 transitions. Our method also found several bugs during the verification process.


2012 ◽  
Vol 241-244 ◽  
pp. 3020-3025
Author(s):  
Ling Ling Dong ◽  
Yong Guan ◽  
Xiao Juan Li ◽  
Zhi Ping Shi ◽  
Jie Zhang ◽  
...  

Considerable attention has been devoted to prove the correctness of programs. Formal verification overcomes the incompleteness by applying mathematical methods to verify a design. SpaceWire is a well known communication standard. For safety-critical applications an approach is needed to validate the completeness of SpareWire design. This paper addresses formal verification of SpareWire error detection module. The system model was constructed by Kripke structure, and the properties were presented by linear temporal logic (LTL). Compared the verification of LTL with CTL (branch temporal logic), LTL properties could improve the verification efficiency due to its linear search. The error priority was checked using simulation guided by model checking. After some properties were modified, all possible behaviors of the module satisfied the specification. This method realizes complete validation of the error detection module.


1990 ◽  
Vol 20 (8) ◽  
pp. 799-821 ◽  
Author(s):  
Louise E. Moser ◽  
P. M. Melliar-Smith

1999 ◽  
Vol 4 (2) ◽  
pp. 123-193 ◽  
Author(s):  
Christoph Kern ◽  
Mark R. Greenstreet

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