Bubble-Proof Algorithm for Wave Union TDCs

Nowadays state-of-the-art time-to-digital converters (TDCs) are commonly implemented in field-programmable gate array (FPGA) devices using different variations of the wave union method. To take full advantage of this method many design challenges need to be overcome, one of which is an efficient data encoding. In this work, we describe in detail an effective algorithm to decode raw output data from a newly designed multisampling wave union TDC. The algorithm is able to correct bubble errors and detect any number of transitions, which occur in the wave union TDC output code. This allows us to reach a mean resolution as high as 0.39 ps and a single shot precision of 2.33 ps in the Xilinx Kintex-7 FPGA chip. The presented algorithm can be used for any kind of wave union TDCs and is intended for partial hardware implementation.

Routing Density Analysis of Area-Efficient Ring Oscillator Physically Unclonable Functions

The research into ring oscillator physically unclonable functions (RO-PUF) continues to expand due to its simple structure, ease of generating responses, and its promises of primitive security. However, a substantial study has yet to be carried out in developing designs of the FPGA-based RO-PUF, which effectively balances performance and area efficiency. This work proposes a modified RO-PUF where the ring oscillators are connected directly to the counters. The proposed RO-PUF requires fewer RO than the conventional structure since this work utilizes the direct pulse count method. This work aims to seek the ideal routing density of ROs to improve uniqueness. For this purpose, five logic arrangements of a wide range of routing densities of ROs were tested. Upon implementation onto the FPGA chip, the routing density of ROs are varied significantly in terms of wire utilization (higher than 25%) and routing hotspots (higher than 80%). The best uniqueness attained was 52.71%, while the highest reliability was 99.51%. This study improves the uniqueness by 2% subsequent to the application of scenarios to consider ROs with a narrow range of routing density. The best range of wire utilization and routing hotspots of individual RO in this work is 3–5% and 20–50%, respectively. The performance metrics (uniqueness and reliability) of the proposed RO-PUF are much better than existing works using a similar FPGA platform (Altera), and it is as good as the recent RO-PUFs realized on Xilinx. Additionally, this work estimates the minimum runtimes to reduce error and response bit-flip of RO-PUF.

FPGA implementation of Lempel-Ziv data compression

When transmitting the data in digital communication, it is well desired that the transmitting data bits should be as minimal as possible, so many techniques are used to compress the data. In this paper, a Lempel-Ziv algorithm for data compression was implemented through VHDL coding. One of the most lossless data compression algorithms commonly used is Lempel-Ziv. The work in this paper is devoted to improve the compression rate, space-saving, and utilization of the Lempel-Ziv algorithm using a systolic array approach. The developed design is validated with VHDL simulations using Xilinx ISE 14.5 and synthesized on Virtex-6 FPGA chip. The results show that our design is efficient in providing high compression rates and space-saving percentage as well as improved utilization. The Throughput is increased by 50% and the design area is decreased by more than 23% with a high compression ratio compared to comparable previous designs.

Development of Low-Resolution, Low-Power and Low-Cost Infrared System

The article presents the construction of a thermal imaging camera with low power consumption. The 80 × 80 Micro80Gen2 microbolometric array of detectors records infrared radiation in the LWIR spectral range (long infrared wave, 8–12 µm). The entire digital part of the electronic circuit has been integrated within the reprogrammable FPGA chip from the Spartan 6 family. In order to read and display thermograms, an application for the .NetFremework 3.1 platform, which implements non-uniformity correction (NUC) and image processing, is written. Due to its low cost, small size and weight, the camera can be used in various applications, e.g. in unmanned aerial vehicles (UAV) known as drones.

Design of a discrete сosine transformation processor for image compression systems on a losless-to-lossy circuit

Today, mobile multimedia systems that use the H.261 / 3/4/5, MPEG-1/2/4 and JPEG standards for encoding / decoding video, audio and images are widely spread [1–4]. The core of these standards is the discrete cosine transform (DCT) of I, II, III ... VIII types [DCT]. Wide support in a huge number of multimedia applications of the JPEG format by circuitry and software solutions and the need for image coding according to the L2L scheme determines the relevance of the problem of creating a decorrelated transformation based on DCT and methods for rapid prototyping of processors for computing an integer DCT on programmable systems on a FPGA chip. At the same time, such characteristics as structural regularity, modularity, high computational parallelism, low latency and power consumption are taken into account. Direct and inverse transformation should be carried out according to the “whole-to-whole” processing scheme with preservation of the perfective reconstruction of the original image (the coefficients are represented by integer or binary rational numbers; the number of multiplication operations is minimal, if possible, they are excluded from the algorithm). The wellknown integer DCTs (BinDCT, IntDCT) do not give a complete reversible bit to bit conversion. To encode an image according to the L2L scheme, the decorrelated transform must be reversible and implemented in integer arithmetic, i. e. the conversion would follow an “integer-to-integer” processing scheme with a minimum number of rounding operations affecting the compactness of energy in equivalent conversion subbands. This article shows how, on the basis of integer forward and inverse DCTs, to create a new universal architecture of decorrelated transform on FPGAs for transformational image coding systems that operate on the principle of “lossless-to-lossy” (L2L), and to obtain the best experimental results for objective and subjective performance compared to comparable compression systems.

A high performance scalable fuzzy based modified Asymmetric Heterogene Multiprocessor System on Chip (AHt-MPSOC) reconfigurable architecture

This Ensuing generation of FPGA circuit tolerates the combination of lot of hard and soft cores as well as devoted accelerators on a chip. The Heterogene Multi-Processor System-on-Chip (Ht-MPSoC) architecture accomplishes the requirement of modern applications. A compound System on Chip (SoC) system designed for single FPGA chip, and that considered for the performance/power consumption ratio. In the existing method, a FPGA based Mixed Integer Programming (MIP) model used to define the Ht-MPSoC configuration by taking into consideration the sharing hardware accelerator between the cores. However, here, the sharing method differs from one processor to another based on FPGA architecture. Hence, high number of hardware resources on a single FPGA chip with low latency and power targeted. For this reason, a fuzzy based MIP and Graph theory based Traffic Estimator (GTE) are proposed system used to define New asymmetric multiprocessor heterogene framework on microprocessor (AHt-MPSoC) architecture. The bandwidths, energy consumption, wait and transmission range are better accomplished in this suggested technique than the standard technique and it is also implemented with a multi-task framework. The new Fuzzy control-based AHt-MPSoC analysis proves significant improvement of 14.7 percent in available bandwidth and 89.8 percent of energy minimized to various traffic scenarios as compared to conventional method.

Design of probe for NQR/NMR detection

Nuclear Magnetic Resonance (NMR) is a RF technique that is able to detect any compound by sensing the excited resonance signals from atomic nuclei having non-zero spin. NQR is similar to NMR but the only difference is NMR needs a DC magnetic field and due to this its application in the field is limited. A FPGA based NQR spectrometer is designed using a single FPGA chip to perform the digital tasks required for NQR spectrometer. Design of Probe for NMR/NQR spectrometer is researched. Parallel tuned and series tuned Probes are discussed and simulated.14N NQR from NaNO2 is observed from spectrometer designed with parallel tuned probe.