High-Speed Single Precision Floating Point Multiplier using CORDIC Algorithm

2018 ◽  
Author(s):  
Balaji Yeshwanth ◽  
Vutukuri Venkatesh ◽  
Repala Akhil
Keyword(s):  
High Speed ◽  
Floating Point ◽  
Cordic Algorithm ◽  
Single Precision

scholarly journals An FPGA-based single-precision floating-point 2048-points FFT implementation based on adaptive angle recoding CORDIC

2017 ◽  
Vol 1 (T4) ◽  
pp. 172-179
Author(s):  
Quynh Thi Nhu Truong ◽  
Thao Thi Phuong Vo ◽  
Thuc Trong Hoang
Keyword(s):  
Mean Square Error ◽  
Floating Point ◽  
Cordic Algorithm ◽  
Mean Square ◽  
Maximum Frequency ◽  
Single Precision ◽  
Fpga Chip

In this paper, an FPGA-based single-precision floating-point 2048-point FFT implementation is proposed, based on an adaptive angle recoding CORDIC algorithm. The design is built and verified on Altera Stratix V FPGA chip. The implementation had 102.55 MHz maximum frequency, throughput result of 8424.382 FFTs/s, and resources utilization of 76,282 ALUTs and 15,687 registers. The accuracy results were 5.889E-06 (Mean-Square-Error (MSE).

A FPGA-Based Design of Floating-Point FFT Processor with Dual-Core

2013 ◽  
Vol 811 ◽  
pp. 441-446
Author(s):  
Jun Ding ◽  
Na Li
Keyword(s):  
Fourier Transform ◽  
High Speed ◽  
Complex Multiplication ◽  
Floating Point ◽  
System Throughput ◽  
Cordic Algorithm ◽  
Clock Frequency ◽  
Sample Number ◽  
Fft Processor ◽  
Dual Core

This paper presents a dual-core floating point FFT processor design based on CORDIC algorithm, enabling high-speed floating-point real-time FFT computation, and its time complexity is (N / 4) Log (N / 2). The design unifiesthe floating complex multiplication and the evaluationof twiddle factors into an iteration, which not only reduces the complexity of complex multiplication but also reduces the difficulty when the butterfly unit deals with floating-point in fast Fourier transform. The butterfly unit unaffected by the size of external memory can handle the Fourier transform with high sample number, both having wider handling range and high handling precision. It uses two logical cores and pipeline technology to improve overall system throughput, with simple hardware structure and system stability.At the end, it does the post-simulation on the Altera chip EP2C35F672C6, and its timing simulation can be run properly under the 50 MHz clock frequency.

scholarly journals Design and Implementation of FPU for Optimised Speed

2020 ◽  
Vol 9 (3) ◽  
pp. 3922-3933
Keyword(s):  
Energy Efficient ◽  
High Speed ◽  
Software Tool ◽  
Digital Signal ◽  
Floating Point ◽  
Double Precision ◽  
Arithmetic Unit ◽  
Single Precision ◽  
Point Multiplication ◽  
Floating Point Unit

Currently, each CPU has one or additional Floating Point Units (FPUs) integrated inside it. It is usually utilized in math wide-ranging applications, such as digital signal processing. It is found in places be established in engineering, medical and military fields in adding along to in different fields requiring audio, image or video handling. A high-speed and energy-efficient floating point unit is naturally needed in the electronics diligence as an arithmetic unit in microprocessors. The most operations accounting 95% of conformist FPU are multiplication and addition. Many applications need the speedy execution of arithmetic operations. In the existing system, the FPM(Floating Point Multiplication) and FPA(Floating Point Addition) have more delay and fewer speed and fewer throughput. The demand for high speed and throughput intended to design the multiplier and adder blocks within the FPM (Floating point multiplication)and FPA(Floating Point Addition) in a format of single precision floating point and double-precision floating point operation is internally pipelined to achieve high throughput and these are supported by the IEEE 754 standard floating point representations. This is designed with the Verilog code using Xilinx ISE 14.5 software tool is employed to code and verify the ensuing waveforms of the designed code

scholarly journals Design of High Speed 32-bit Floating Point Multiplier using Urdhva Triyagbhyam Sutra of Vedic Mathematics

2019 ◽  
Vol 8 (2S3) ◽  
pp. 1064-1067
Keyword(s):  
High Speed ◽  
Floating Point ◽  
Single Precision ◽  
Point Multiplication ◽  
Vedic Mathematics ◽  
Design And Implementation ◽  
Minimum Delay ◽  
Dsp Applications

Multiplication of floating point(FP) numbers is greatly significant in many DSP applications. The performance of the DSP’s is substantially decided by the speed of the multipliers used. This paper proposes the design and implementation of IEEE 754 standard single precision FP multiplier using Verilog, synthesized and simulated in Xilinx ISE10.1. Urdhva Triyagbhyam Sutra of Vedic mathematics is used for the unsigned mantissa calculation. The design implements floating point multiplication with sign bit and exponent calculations. The proposed design is achieved high speed with minimum delay of 3.997ns.Multiplication of floating point(FP) numbers is greatly significant in many DSP applications. The performance of the DSP’s is substantially decided by the speed of the multipliers used. This paper proposes the design and implementation of IEEE 754 standard single precision FP multiplier using Verilog, synthesized and simulated in Xilinx ISE10.1. Urdhva Triyagbhyam Sutra of Vedic mathematics is used for the unsigned mantissa calculation. The design implements floating point multiplication with sign bit and exponent calculations. The proposed design is achieved high speed with minimum delay of 3.997ns.

scholarly journals DESIGN OF A HIGH-SPEED HIGH-ACCURACY 2048-POINT FFT USING SINGLE-PRECISION FLOATING-POINT ADAPTIVE CORDIC ON FPGA

2018 ◽  
Vol 56 (6) ◽  
pp. 751
Author(s):  
Duc Hung Le
Keyword(s):  
Fourier Transform ◽  
Fast Fourier Transform ◽  
High Speed ◽  
High Accuracy ◽  
Experimental Results ◽  
Floating Point ◽  
Path Delay ◽  
Single Precision ◽  
Look Up Table ◽  
Speed Performance

In this paper, hardware design of a Fast Fourier Transform (FFT) core using Single-precision Floating-point Adaptive CORDIC is implemented on Altera Stratix IV FPGA. With FFT implementation, CORDIC is utilized for reducing the speed drawback of complex multiplication and the adaptive algorithm is proposed to decrease the iterations of conventional CORDIC. The experimental results of Adaptive CORDIC and 2048-point Radix-2 Multi-path Delay Commutator FFT designs are built and verified based on three kinds of Look-up Table that cost 16, 8 and 4 constant angles. As experimental results, there is a resource equivalence while it has a trade-off between speed performance and accuracy. In comparison, an adaptive CORDIC core based on Look-up Table of 16 constant angles, and 2048-point Radix-2 Multi-path Delay Commutator Fast Fourier Transform based on Adaptive CORDIC using Look-up Table of 16 constant angles are well responding to resource optimization, high-speed performance and high-accuracy of computations.

Dual-Core FFT Processor Based on a High-Speed Real-Time Floating-Point Butterfly Processing Element

2014 ◽  
Vol 513-517 ◽  
pp. 1034-1037
Author(s):  
Jun Yang ◽  
Yan Yan Yu ◽  
Qian Huang ◽  
Wen Long Li
Keyword(s):  
High Speed ◽  
Complex Multiplication ◽  
Floating Point ◽  
Cordic Algorithm ◽  
Pipeline System ◽  
Fft Processor ◽  
Computation Process ◽  
Large Scope ◽  
Timing Simulation ◽  
Dual Core

This paper presents a dual-core floating-point FFT processor. The internal butterfly unit of the processor based on CORDIC algorithm, and uses an iterative computation process instead of two computation process which is the complex multiplication and the evaluation of trigonometric function. The butterfly unit has nothing to do with the external memory size, so it can handle large quantities of data. Based on this unit, the processor uses two logical processing core and pipeline system to improve the throughput and instantaneity. So the design has large scope of input and high-precision operation features. Finally, we make a timing simulation for the Alteras chip of EP2C20F484C6, which can run correctly under the 100MHz system clock.

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