Design and Evaluation of a Power-Efficient Approximate Systolic Array Architecture for Matrix Multiplication

2019 IEEE International Workshop on Signal Processing Systems (SiPS) ◽

10.1109/sips47522.2019.9020404 ◽

2019 ◽

Author(s):

Haroon Waris ◽

Chenghua Wang ◽

Weiqiang Liu ◽

Fabrizio Lombardi

Keyword(s):

Systolic Array ◽

Matrix Multiplication ◽

Power Efficient ◽

Array Architecture

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Design and FPGA Implementation of Systolic Array Architecture for Matrix Multiplication

International Journal of Computer Applications ◽

10.5120/3084-4222 ◽

2011 ◽

Vol 26 (3) ◽

pp. 18-22 ◽

Author(s):

Mahendra Vucha ◽

Arvind Rajawat

Keyword(s):

Systolic Array ◽

Matrix Multiplication ◽

Fpga Implementation ◽

Array Architecture

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A Novel Systolic Array Architecture for Matrix Multiplication Circuit Design using Carbon Nanotube Technology

International Journal of Computer Applications ◽

10.5120/ijca2017915156 ◽

2017 ◽

Vol 172 (6) ◽

pp. 1-4

Author(s):

Alireza Azimian ◽

Ali Kargaran ◽

Mohammad Tehrani

Keyword(s):

Carbon Nanotube ◽

Circuit Design ◽

Systolic Array ◽

Matrix Multiplication ◽

Array Architecture ◽

Carbon Nanotube Technology

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A three dimensional systolic array architecture for fast matrix multiplication

10.1109/icassp.1984.1172607 ◽

2005 ◽

Author(s):

R. Linderman ◽

W. Ku

Keyword(s):

Systolic Array ◽

Matrix Multiplication ◽

Three Dimensional ◽

Fast Matrix Multiplication ◽

Array Architecture

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Improved Design and Analyse of Parallel Matrix Multiplication on Systolic Array Matrix

2009 International Conference on Computational Intelligence and Software Engineering ◽

10.1109/cise.2009.5366384 ◽

2009 ◽

Author(s):

Feifei Dong ◽

Sihan Zhang ◽

Cheng Chen

Keyword(s):

Systolic Array ◽

Matrix Multiplication ◽

Improved Design

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A scalable systolic array architecture for the 2D discrete wavelet transform

38th Midwest Symposium on Circuits and Systems. Proceedings ◽

10.1109/mwscas.1995.510290 ◽

2002 ◽

Author(s):

Jijun Chen ◽

M.A. Bayoumi

Keyword(s):

Wavelet Transform ◽

Discrete Wavelet Transform ◽

Systolic Array ◽

Discrete Wavelet ◽

Array Architecture

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A systolic array architecture for the Applebaum-Howells array

IEEE Transactions on Antennas and Propagation ◽

10.1109/8.56974 ◽

1990 ◽

Vol 38 (8) ◽

pp. 1310-1313 ◽

Author(s):

M. Ueno ◽

K. Kawabata ◽

T. Morooka

Keyword(s):

Systolic Array ◽

Array Architecture

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A 2 1/2 -dimensional systolic array architecture

Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94 ◽

10.1109/iscas.1994.409242 ◽

2002 ◽

Author(s):

S.P.S. Lam

Keyword(s):

Systolic Array ◽

Array Architecture

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Systolic-array architecture for 2D IIR Wideband dual-beam space-time plane-wave filters

2010 53rd IEEE International Midwest Symposium on Circuits and Systems ◽

10.1109/mwscas.2010.5548677 ◽

2010 ◽

Author(s):

Chamith Wijenayake ◽

Arjuna Madanayake ◽

Len T. Bruton

Keyword(s):

Systolic Array ◽

Dual Beam ◽

Array Architecture ◽

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A systolic array architecture for image coding using vector quantization

10.1109/vtsa.1989.68628 ◽

2003 ◽

Author(s):

S. Panchanathan ◽

M. Goldberg

Keyword(s):

Vector Quantization ◽

Systolic Array ◽

Image Coding ◽

Array Architecture

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Compact FPGA-based systolic array architecture suitable for vision systems

Fourth International Conference on Information Technology (ITNG'07) ◽

10.1109/itng.2007.209 ◽

2007 ◽

Author(s):

Griselda Saldana ◽

Miguel Arias-Estrada

Keyword(s):

Systolic Array ◽

Vision Systems ◽

Array Architecture

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