AbstractIt is clear that, at the device level, CMOS is scaleable to 0.1 μm and beyond, provided that the power supply voltage and the device physical dimensions are reduced in some coordinated manner. Contacting these devices and connecting them into circuits, and wiring the circuits at the chip level will become ever more challenging. Furthermore, the integration level of 0.1-μm technology is such that the chip will be the system or at least the core of the system. Thus, the BEOL will not be just for interconnecting the circuits on the chip, but provide the interconnect functions that are presently on the package and/or the board. To this end, copper and low-ε inter-level dielectric, on-chip decoupling capacitor, as well as wire-level hierarchy, will be needed.
