Adaptive Internal Clock Synchronization

Author(s):  
Zbigniew Jerzak ◽  
Robert Fach ◽  
Christof Fetzer
2010 ◽  
Vol 21 (5) ◽  
pp. 607-619 ◽  
Author(s):  
Roberto Baldoni ◽  
Angelo Corsaro ◽  
Leonardo Querzoni ◽  
Sirio Scipioni ◽  
Sara Tucci Piergiovanni

2021 ◽  
Vol 2108 (1) ◽  
pp. 012092
Author(s):  
Hongbo Lian ◽  
Xingcai Wang ◽  
Shuo Zhang

Abstract This paper introduces the problems of poor signal condition of a single time source in time synchronization or error in time source switching in the power system. It adopts the two-clock mode timing scheme of BeiDou 2 synchronous satellite and GPS synchronous satellite to ensure the stable output of the main clock within a certain accuracy. The system takes full advantage of the field programmable gate array (FPGA) hardware method, aligns the internal clock lock signal with the input second pulse phase, and proposes an improved method for the problem of large clock synchronization deviation based on the network, which proves the effectiveness and superiority of the system to accurately output the pulse and provide reliable time synchronization for the power dispatching system.


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