Low-Cost Hybrid Internal Clock Synchronization Mechanism for COTS PC Cluster

Author(s):  
Jorji Nonaka ◽  
Gerson H. Pfitscher ◽  
Katsumi Onisi ◽  
Hideo Nakano
2018 ◽  
Vol 8 (3) ◽  
pp. 26
Author(s):  
Paul Milbredt ◽  
Efim Schick ◽  
Michael Hübner

Modern automotive control applications require a holistic time-sensitive development. Nowadays, this is achieved by technologies specifically designed for the automotive domain, like FlexRay, which offer a fault-tolerant time synchronization mechanism built into the protocol. Currently, the automotive industry adopts the Ethernet within the car, not only for embedding consumer electronics, but also as a fast and reliable backbone for control applications. Still, low-cost but highly reliable sensors connected over the traditional Controller Area Network (CAN) deliver data needed for autonomous driving. To fusion the data efficiently among all, a common timebase is required. The alternative would be oversampling, which uses more time and energy, e.g., at least double the perception rates of sensors. Ethernet and CAN do require the latter by default. Hence, a global synchronization mechanism eases tremendously the design of a low power automotive network and is the foundation of a transparent global clock. In this article, we present the first step: Synchronizing legacy FlexRay networks to the upcoming Ethernet backbone, which will contain a precise clock over the generalized Precision Time Protocol (gPTP) defined in IEEE 802.1AS. FlexRay then could still drive its strengths with deterministic transmission behavior and possibly also serve as a redundant technology for fail-operational system design.


2016 ◽  
Vol 78 (5-9) ◽  
Author(s):  
Ronnie O. Serfa Juan ◽  
Hi Seok Kim

Advanced driver assistance system (ADAS) performs an increasing improvement in active road safety and driving convenience. Controller Area Network (CAN) is now getting popular because of its expanding applications and widely utilizations in low-cost embedded systems from automation to medical industry. While implementing an effective and efficient mechanism for clock synchronization, serial operation causes the reduction of CAN transmission rate can have an adverse impact on the real-time applications of systems employing this protocol. Also, maintaining the reliability of this technology especially in safety services, a reliable system needs certain requirements like glitches management and troubleshooting in order to avoid certain occurrences of transmission error.  In this paper we present a simulated Cyclic Redundancy Checking (CRC) encoder and decoder that perform high speed error detection for CAN using CRC-15. Digital Signal Processing (DSP) algorithms were used, namely pipelining, unfolding and retiming to attain the feasible iteration bound and critical path that is appropriate for CAN system. The source code for Encoder and Decoder has been formulated in Verilog Hardware Description Language (HDL) from actual simulation to implementation of this CRC-15 for CAN system.


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