A 25mW Highly Linear Continuous-Time FIR Equalizer for 25Gb/s Serial Links in 28-nm CMOS

2017 ◽  
Vol 64 (7) ◽  
pp. 1903-1913 ◽  
Author(s):  
Fabrizio Loi ◽  
Enrico Mammei ◽  
Simone Erba ◽  
Matteo Bassi ◽  
Andrea Mazzanti
Keyword(s):  
Continuous Time ◽  
Serial Links ◽  
28 Nm

A Continuous-Time 0–3 MASH ADC Achieving 88 dB DR With 53 MHz BW in 28 nm CMOS

2014 ◽  
Vol 49 (12) ◽  
pp. 2868-2877 ◽  
Author(s):  
Yunzhi Dong ◽  
William Yang ◽  
Richard Schreier ◽  
Ali Sheikholeslami ◽  
Sudhir Korrapati
Keyword(s):  
Continuous Time ◽  
28 Nm

A 2–11 GHz 7-Bit High-Linearity Phase Rotator Based on Wideband Injection-Locking Multi-Phase Generation for High-Speed Serial Links in 28-nm CMOS FDSOI

2017 ◽  
Vol 52 (7) ◽  
pp. 1739-1752 ◽  
Author(s):  
Enrico Monaco ◽  
Gabriele Anzalone ◽  
Guido Albasini ◽  
Simone Erba ◽  
Matteo Bassi ◽  
...  
Keyword(s):  
High Speed ◽  
Injection Locking ◽  
Serial Links ◽  
High Linearity ◽  
Multi Phase ◽  
Phase Rotator ◽  
28 Nm

A multi-rate continuous-time adaptive equalizer for high-speed serial links

2015 ◽  
Author(s):  
E. Guerrero ◽  
C. Gimeno ◽  
C. Sánchez-Azqueta ◽  
J. Aguirre ◽  
S. Celma
Keyword(s):  
Continuous Time ◽  
High Speed ◽  
Serial Links ◽  
Adaptive Equalizer

A 7-GS/s 5-Bit Continuous-Time Pipelined Binary-Search Flash ADC in 28-nm CMOS

2020 ◽  
Vol 3 ◽  
pp. 366-369
Author(s):  
Danial Mohammadi ◽  
M. Wagih Ismai ◽  
Rudraneil Saha ◽  
Hajime Shibata ◽  
Zhao Li ◽  
...  
Keyword(s):  
Continuous Time ◽  
Binary Search ◽  
Flash Adc ◽  
28 Nm

A Continuous-Time Sturdy-MASH $\Delta\Sigma$ Modulator in 28 nm CMOS

2015 ◽  
Vol 50 (12) ◽  
pp. 2880-2890 ◽  
Author(s):  
Do-Yeon Yoon ◽  
Stacy Ho ◽  
Hae-Seung Lee
Keyword(s):  
Continuous Time ◽  
Delta Sigma ◽  
28 Nm

EQUALIZERS FOR HIGH-SPEED SERIAL LINKS

2005 ◽  
Vol 15 (02) ◽  
pp. 429-458 ◽  
Author(s):  
PAVAN KUMAR HANUMOLU ◽  
GU-YEON WEI ◽  
UN-KU MOON
Keyword(s):  
Continuous Time ◽  
High Speed ◽  
Decision Feedback ◽  
Decision Feedback Equalizer ◽  
Serial Links ◽  
Communication Links ◽  
Inter Symbol Interference

In this tutorial paper we present equalization techniques to mitigate inter-symbol interference (ISI) in high-speed communication links. Both transmit and receive equalizers are analyzed and high-speed circuits implementing them are presented. It is shown that a digital transmit equalizer is the simplest to design, while a continuous-time receive equalizer generally provides better performance. Decision feedback equalizer (DFE) is described and the loop latency problem is addressed. Finally, techniques to set the equalizer parameters adaptively are presented.

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