flash adc
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Ahmed Ansari ◽  
Khan Rizwan ◽  
Mohammed Fawzaan Roghay ◽  
Shaikh Faisal ◽  
Sudhakar Mande

2021 ◽  
Vol 21 (5) ◽  
pp. 142-149
Jelena Jovanović ◽  
Dragan Denić

Abstract Pt100 is a resistance temperature detector characterized by a relatively linear resistance/temperature relationship in a narrow temperature range. However, the Pt100 sensor shows a certain degree of static transfer function nonlinearity of 4.42 % in the range between −200 °C and 850 °C, which is unacceptable for some applications. As a solution to this problem, a mixed-mode linearization method based on a special dual-stage piecewise linear ADC design is proposed in this paper. The first stage of the proposed dual-stage piecewise linear ADC is performed with a low-complex and low-power flash ADC of a novel sequential design. The novelty of the proposed sequential design is reflected in the fact that the number of employed comparators is equal to the flash ADC resolution. The second stage is performed with a delta-sigma ADC with a differential input and differential reference. Using the 6-bit flash ADC of novel design and the 24-bit delta-sigma ADC, the nonlinearity error is reduced to 2.6·10−3 %, in the range between −200 °C and 850 °C. Two more ranges are examined, and the following results are obtained: in the range between 0 °C and 500 °C, the nonlinearity error is reduced from 1.99 % to 5·10−4 %, while in the range between −50 °C and 150 °C, the nonlinearity error is reduced from 0.755 % to 2.15·10−4 %.

2021 ◽  
Vol 13 ◽  
Banoth Krishna ◽  
Sandeep Singh Gill ◽  
Amod Kumar

: This work reviews the design challenges of CMOS flash type analog-to-digital converter (ADC) for making high bit resolution, low area, low noise, low offset, and power-efficient architecture. Low-bit resolution flash ADC architecture, high-speed applications, and wide-area parallel comparators are identified on their suitability of the design for ADCs. These are effective in the area and bit resolution. The overview includes bit resolution, area, power dissipation, bandwidth and offset noise consideration for high-speed flash ADC design. A MUX-based two-step half flash architecture is considered for applications requiring 1 GHz 16-bit resolution low area and low power consumption. An advanced comparator, MUX, a high-speed digital-to-analog converter(DAC), and MUX-based encoder are also reviewed. The design of technology-efficient ADC architecture is highly challenging for the analog designer.

Navneet Gupta ◽  
Hitesh Shrimali ◽  
Adam Makosiej ◽  
Andrei Vladimirescu ◽  
Amara Amara

2021 ◽  
Vol 31 (5) ◽  
pp. 1-4
Delaramsadat Ghadri ◽  
Ashish Shukla ◽  
Amol Inamdar ◽  
Raafat R. Mansour

2021 ◽  
Shatadal Chatterjee ◽  
Maryaradhiya Daimari ◽  
Sounak Roy

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