Validating the performance of a 32nm CMOS high speed serial link receiver with adaptive equalization and baud-rate clock data recovery

2010 IEEE International Test Conference ◽

10.1109/test.2010.5699242 ◽

2010 ◽

Author(s):

Sudeep Puligundla ◽

Fulvio Spagna ◽

Lidong Chen ◽

Amanda Tran

Keyword(s):

Data Recovery ◽

Adaptive Equalization ◽

Serial Link ◽

Baud Rate ◽

Clock Data Recovery

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A 40 Gb/s CMOS Serial-Link Receiver With Adaptive Equalization and Clock/Data Recovery

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2008.2005535 ◽

2008 ◽

Vol 43 (11) ◽

pp. 2492-2502 ◽

Author(s):

Chih-Fan Liao ◽

Shen-Iuan Liu

Keyword(s):

Data Recovery ◽

Adaptive Equalization ◽

Serial Link ◽

Clock Data Recovery

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6.2 A 60Gb/s 288mW NRZ transceiver with adaptive equalization and baud-rate clock and data recovery in 65nm CMOS technology

2017 IEEE International Solid-State Circuits Conference (ISSCC) ◽

10.1109/isscc.2017.7870286 ◽

2017 ◽

Author(s):

Jaeduk Han ◽

Yue Lu ◽

Nicholas Sutardja ◽

Elad Alon

Keyword(s):

Clock And Data Recovery ◽

Cmos Technology ◽

Data Recovery ◽

Adaptive Equalization ◽

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Adaptive equalization and data recovery in a dual-mode (PAM2/4) serial link transceiver

2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525) ◽

10.1109/vlsic.2004.1346611 ◽

2004 ◽

Author(s):

V. Stojanovic ◽

A. Ho ◽

B. Garlepp ◽

F. Chen ◽

J. Wei ◽

...

Keyword(s):

Data Recovery ◽

Adaptive Equalization ◽

Dual Mode ◽

Serial Link ◽

Serial Link Transceiver

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Multi-rate Clock-Data recovery solution in high speed serial links

2015 IEEE 35th International Conference on Electronics and Nanotechnology (ELNANO) ◽

10.1109/elnano.2015.7146883 ◽

2015 ◽

Author(s):

Melikyan Vazgen ◽

Sahakyan Arthur ◽

Shishmanyan Aram ◽

Hekimyan Arsen

Keyword(s):

Data Recovery ◽

Serial Links ◽

Clock Data Recovery

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Design Techniques for a 60-Gb/s 288-mW NRZ Transceiver With Adaptive Equalization and Baud-Rate Clock and Data Recovery in 65-nm CMOS Technology

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2017.2740268 ◽

2017 ◽

Vol 52 (12) ◽

pp. 3474-3485 ◽

Author(s):

Jaeduk Han ◽

Nicholas Sutardja ◽

Yue Lu ◽

Elad Alon

Keyword(s):

Clock And Data Recovery ◽

Cmos Technology ◽

Data Recovery ◽

Adaptive Equalization ◽

Baud Rate ◽

Design Techniques

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High-speed baud-rate clock and data recovery

2007 7th International Conference on ASIC ◽

10.1109/icasic.2007.4415568 ◽

2007 ◽

Author(s):

Faisal A. Musa ◽

Anthony Chan Carusone

Keyword(s):

Clock And Data Recovery ◽

Data Recovery ◽

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A 10-Gb/s CMOS Serial-Link Receiver using Eye-Opening Monitoring for Adaptive Equalization and for Clock and Data Recovery

2007 IEEE Custom Integrated Circuits Conference ◽

10.1109/cicc.2007.4405732 ◽

2007 ◽

Author(s):

Thomas Suttorp ◽

Ulrich Langmann

Keyword(s):

Clock And Data Recovery ◽

Data Recovery ◽

Adaptive Equalization ◽

Serial Link ◽

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A power and area efficient CMOS clock/data recovery circuit for high-speed serial interfaces

IEEE Journal of Solid-State Circuits ◽

10.1109/4.508265 ◽

1996 ◽

Vol 31 (8) ◽

pp. 1170-1176 ◽

Author(s):

Dao-Long Chen

Keyword(s):

Data Recovery ◽

Clock Data Recovery ◽

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Autonomous dual-mode (PAM2/4) serial link transceiver with adaptive equalization and data recovery

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2004.842863 ◽

2005 ◽

Vol 40 (4) ◽

pp. 1012-1026 ◽

Author(s):

V. Stojanovic ◽

A. Ho ◽

B.W. Garlepp ◽

F. Chen ◽

J. Wei ◽

...

Keyword(s):

Data Recovery ◽

Adaptive Equalization ◽

Dual Mode ◽

Serial Link ◽

Serial Link Transceiver

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A Low Noise Fault Tolerant Radiation Hardened 2.56 Gbps Clock-Data Recovery Circuit With High Speed Feed Forward Correction in 65 nm CMOS

IEEE Transactions on Circuits and Systems I Regular Papers ◽

10.1109/tcsi.2019.2944791 ◽

2020 ◽

Vol 67 (5) ◽

pp. 1438-1446 ◽

Author(s):

Stefan Biereigel ◽

Szymon Kulis ◽

Pedro Leitao ◽

Rui Francisco ◽

Paulo Moreira ◽

...

Keyword(s):

Fault Tolerant ◽

Low Noise ◽

Data Recovery ◽

Feed Forward ◽

Clock Data Recovery ◽

Radiation Hardened

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