scholarly journals A Monolithic 3D Hybrid Architecture for Energy-Efficient Computation

2018 ◽  
Vol 4 (4) ◽  
pp. 533-547 ◽  
Author(s):  
Ye Yu ◽  
Niraj K. Jha

in our manuscript, various circuits for arithmetic summation are compared. Cadence 90nm technology and Quartus II EP2C20F484C7 are used for implementation of design. Logic gate-based adders, PFCA, TG and HSD technique-based adders characteristics are analyzed. Y finding is PFCA with 10T transistor performs slightly efficient compare to its counterpart. Exclusive OR-NOR design is optimum for least delay Adders for high performance energy efficient processing unit.


IEEE Access ◽  
2019 ◽  
Vol 7 ◽  
pp. 68656-68668 ◽  
Author(s):  
Ang Gao ◽  
Yansu Hu ◽  
Wei Liang ◽  
Yizhi Lin ◽  
Lixin Li ◽  
...  

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