A comprehensive analysis of low-power operation for beacon-enabled IEEE 802.15.4 wireless networks

2009 ◽  
Vol 8 (11) ◽  
pp. 5601-5611 ◽  
Author(s):  
Yu-Kai Huang ◽  
Ai-Chun Pang ◽  
Hui-Nien Hung
Keyword(s):  
Wireless Networks ◽  
Low Power ◽  
Ieee 802.15.4 ◽  
Comprehensive Analysis ◽  
Power Operation

Z-Monitor: A protocol analyzer for IEEE 802.15.4-based low-power wireless networks

2016 ◽  
Vol 95 ◽  
pp. 77-96 ◽  
Author(s):  
Stefano Tennina ◽  
Olfa Gaddour ◽  
Anis Koubâa ◽  
Fernando Royo ◽  
Mário Alves ◽  
...  
Keyword(s):  
Wireless Networks ◽  
Low Power ◽  
Ieee 802.15.4 ◽  
Low Power Wireless Networks ◽  
Protocol Analyzer

A comprehensive analysis of association process for IEEE 802.15.4 wireless networks

2014 ◽  
Vol 16 (1) ◽  
pp. 70 ◽  
Author(s):  
Jo Woon Chong ◽  
Ho Young Hwang ◽  
Dan Keun Sung ◽  
Yunyoung Nam
Keyword(s):  
Wireless Networks ◽  
Ieee 802.15.4 ◽  
Comprehensive Analysis

An Ultra-low Power Consumption MAC Protocol Complied with IEEE 802.15.4/4e for Wireless Smart Utility Networks

2016 ◽  
Vol 136 (11) ◽  
pp. 1555-1566 ◽  
Author(s):  
Jun Fujiwara ◽  
Hiroshi Harada ◽  
Takuya Kawata ◽  
Kentaro Sakamoto ◽  
Sota Tsuchiya ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Ieee 802.15.4 ◽  
Mac Protocol ◽  
Low Power Consumption ◽  
Ultra Low Power

Compact Hardware Implementations of MISTY1 Block Cipher

2017 ◽  
Vol 27 (03) ◽  
pp. 1850037 ◽  
Author(s):  
Yasir ◽  
Ning Wu ◽  
Xiaoqiang Zhang
Keyword(s):  
Low Power ◽  
Block Cipher ◽  
Comprehensive Analysis ◽  
The Other ◽  
Key Generation ◽  
Round Function ◽  
Other Hand ◽  
Hardware Implementations ◽  
Covered Area

This paper proposes compact hardware implementations of 64-bit NESSIE proposed MISTY1 block cipher for area constrained and low power ASIC applications. The architectures comprise only one round MISTY1 block cipher algorithm having optimized FO/FI function by re-utilizing S9/S7 substitution functions. A focus is also made on efficient logic implementations of S9 and S7 substitution functions using common sub-expression elimination (CSE) and parallel AND/XOR gates hierarchy. The proposed architecture 1 generates extended key with independent FI function and is suitable for MISTY1 8-rounds implementation. On the other hand, the proposed architecture 2 uses a single FO/FI function for both MISTY1 round function as well as extended key generation and can be employed for MISTY1 [Formula: see text] rounds. To analyze the performance and covered area for ASICs, Synopsys Design Complier, SMIC 0.18[Formula: see text][Formula: see text]m @ 1.8[Formula: see text]V is used. The hardware constituted 3041 and 2331 NAND gates achieving throughput of 171 and 166 Mbps for 8 rounds implementation of architectures 1 and 2, respectively. Comprehensive analysis of proposed designs is covered in this paper.

A 2.4-GHz Low-Power Low-IF Receiver and Direct-Conversion Transmitter in 0.18-$\mu{\hbox {m}}$ CMOS for IEEE 802.15.4 WPAN Applications

2007 ◽  
Vol 55 (4) ◽  
pp. 682-689 ◽  
Author(s):  
Ilku Nam ◽  
Kyudon Choi ◽  
Joonhee Lee ◽  
Hyouk-Kyu Cha ◽  
Bo-Ik Seo ◽  
...  
Keyword(s):  
Low Power ◽  
Ieee 802.15.4 ◽  
Direct Conversion ◽  
Low If Receiver
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