An N/M-Ratio All-Digital Clock Generator with a Pseudo-NMOS Comparator-Based Programmable Divider

A multiplying delay-locked loop (MDLL)-based all-digital clock generator with a programmable N/M-ratio frequency multiplication capability for digital SoC is presented. The proposed digital MDLL provides programmable N/M-ratio frequency multiplication using a new high-speed Pseudo-NMOS comparator-based programmable divider with small area and low power consumption. The proposed MDLL clock generator can also provide a de-skew function by eliminating the phase offset problem caused by the propagation delay of the front divider in conventional N/M MDLL architectures. Fabricated in a 0.13-µm 1.2-V CMOS process, the proposed digital MDLL clock generates fully de-skewed output clock frequencies from 0.3 to 1.137 GHz with programmable N/M ratios of N = 1~32 and M = 1~16. It achieves a measured effective peak-to-peak jitter of 12 ps at 1.0 GHz when N/M = 8/1. It occupies an active area of only 0.034 mm2 and consumes a power of 10.3 mW at 1.0 GHz.

Lightweight VLSI Architectures for Image Encryption Applications

Lightweight cryptography offers significant security service in constrained environments such as wireless sensor networks and Internet of Things. The focus of this article is to construct lightweight SPN block cipher architectures with substitution box based on finite fields. The paper also details the FPGA implementation of the lightweight symmetric block cipher algorithm of SPN type with combinational S-box. Restructuring of traditional look-up-table Substitution Box (S-Box) sub-structure with a combinational logic S-box is attempted. Elementary architectures namely the basic round architecture and reduced datawidth architecture incorporating look-up-table and combinational S-Box substructure are compared in terms of area and throughput. Proposed restructure mechanism occupies less FPGA resources with no comprise in the latency and also demonstrates performance efficiency and low power consumption in Xilinx FPGAs. Robustness of the proposed method against various statistical attacks has been analyzed through comparison with other existing encryption mechanisms.

Circularly Polarized Luminescent Porous Crystalline Nanomaterials

Circularly polarized luminescence (CPL) active materials have attracted exclusive attention because of their wide potential applications in low-power-consumption displays, encrypted information storage, chiroptical sensors, and so on. However, there is...

Novel Fabrication Technology for Clamped Micron-Thick Titanium Diaphragms Used for the Packaging of an Implantable MEMS Acoustic Transducer

Micro-Electro-Mechanical Systems (MEMS) acoustic transducers are highly sophisticated devices with high sensing performance, small size, and low power consumption. To be applied in an implantable medical device, they require a customized packaging solution with a protecting shell, usually made from titanium (Ti), to fulfill biocompatibility and hermeticity requirements. To allow acoustic sound to be transferred between the surroundings and the hermetically sealed MEMS transducer, a compliant diaphragm element needs to be integrated into the protecting enclosure. In this paper, we present a novel fabrication technology for clamped micron-thick Ti diaphragms that can be applied on arbitrary 3D substrate geometry and hence directly integrated into the packaging structure. Stiffness measurements on various diaphragm samples illustrate that the technology enables a significant reduction of residual stress in the diaphragm developed during its deposition on a polymer sacrificial material.

Pure voltage-driven spintronic neuron based on stochastic magnetization switching behaviour

Voltage-driven stochastic magnetization switching in a nanomagnet has attracted more attention recently with its superiority in achieving energy-efficient artificial neuron. Here, a novel pure voltage-driven scheme with ~27.66 aJ energy dissipation is proposed, which could rotate magnetization vector randomly using only a pair of electrodes covered on the multiferroic nanomagnet. Results show that the probability of 180° magnetization switching is examined as a sigmoid-like function of the voltage pulse width and magnitude, which can be utilized as the activation function of designed neuron. Considering the size errors of designed neuron in fabrication, it’s found that reasonable thickness and width variations cause little effect on recognition accuracy for MNIST hand-written dataset. In other words, the designed pure voltage-driven spintronic neuron could tolerate size errors. These results open a new way toward the realization of artificial neural network with low power consumption and high reliability.

Hardware-Based Activation Function-Core for Neural Network Implementations

Today, embedded systems (ES) tend towards miniaturization and the carrying out of complex tasks in applications such as the Internet of Things, medical systems, telecommunications, among others. Currently, ES structures based on artificial intelligence using hardware neural networks (HNNs) are becoming more common. In the design of HNN, the activation function (AF) requires special attention due to its impact on the HNN performance. Therefore, implementing activation functions (AFs) with good performance, low power consumption, and reduced hardware resources is critical for HNNs. In light of this, this paper presents a hardware-based activation function-core (AFC) to implement an HNN. In addition, this work shows a design framework for the AFC that applies a piecewise polynomial approximation (PPA) technique. The designed AFC has a reconfigurable architecture with a wordlength-efficient decoder, i.e., reduced hardware resources are used to satisfy the desired accuracy. Experimental results show a better performance of the proposed AFC in terms of hardware resources and power consumption when it is compared with state of the art implementations. Finally, two case studies were implemented to corroborate the AFC performance in widely used ANN applications.

Koch Snowflake Fractal Antenna Design in the Deep Space Bands for a Constellation of Cubesat Explorers

This paper presents the design and simulation of a Koch curve fractal antenna, developed according to the second iteration of the Koch snowflake fractal for S-band, C-band, X-band and Ku-band. The simulated antenna shows good performance for the operating frequencies and desirable gain, bandwidth and VSWR parameters. Being a compact antenna, it has a size, geometry and characteristics that go in accord with the CubeSat’s structure standards. The antenna was fabricated on a 1.5 mm thick FR-4 substrate. The VSWR achieved values are lower than 1.4 for the frequencies used (2.1 GHz to 2.4 GHz and 7.4 GHz to 8.9 GHz) with a simulated omnidirectional radiation pattern. A maximum gain of 6.8 dBi was achieved. As this antenna works optimally in the S, C and X bands, it is adequate for deep space applications, especially in low-power consumption systems. This approach would be ideal for constellations of Cubesat explorers.

Reconfigurable Computing for Reactive Robotics Using Open-Source FPGAs

Reconfigurable computing provides a paradigm to create intelligent systems different from the classic software computing approach. Instead of using a processor with an instruction set, a full stack of middleware, and an application program running on top, the field-programmable gate arrays (FPGAs) integrate a cell set that can be configured in different ways. A few vendors have dominated this market with their proprietary tools, hardware devices, and boards, resulting in fragmented ecosystems with few standards and little interoperation. However, a new and complete toolchain for FPGAs with its associated open tools has recently emerged from the open-source community. Robotics is an expanding application field that may definitely benefit from this revolution, as fast speed and low power consumption are usual requirements. This paper hypothesizes that basic reactive robot behaviors may be easily designed following the reconfigurable computing approach and the state-of-the-art open FPGA toolchain. They provide new abstractions such as circuit blocks and wires for building intelligent robots. Visual programming and block libraries make such development painless and reliable. As experimental validation, two reactive behaviors have been created in a real robot involving common sensors, actuators, and in-between logic. They have been also implemented using classic software programming for comparison purposes. Results are discussed and show that the development of reactive robot behaviors using reconfigurable computing and open tools is feasible, also achieving a high degree of simplicity and reusability, and benefiting from FPGAs’ low power consumption and time-critical responsiveness.

Design and Implementation of a Smart Energy Meter Using a LoRa Network in Real Time

Nowadays, the development, implementation and deployment of smart meters (SMs) is increasing in importance, and its expansion is exponential. The use of SMs in electrical engineering covers a multitude of applications ranging from real-time monitoring to the study of load profiles in homes. The use of wireless technologies has helped this development. Various problems arise in the implementation of SMs, such as coverage, locations without Internet access, etc. LoRa (long range) technology has great coverage and equipment with low power consumption that allows the installation of SMs in all types of locations, including those without Internet access. The objective of this research is to create an SM network under the LoRa specification that solves the problems presented by other wireless networks. For this purpose, a gateway for residential electricity metering networks using LoRa (GREMNL) and an electrical variable measuring device for households using LoRa (EVMDHL) have been created, which allow the development of SM networks with large coverage and low consumption.

Implementation of a number recognition algorithm built using a neural network on the BASYS3 FPGA panel

In recent years, some field programmable valve arrays (FPGAs) based on CNN release phase accelerators have been introduced. FPGA is widely used in portable devices. They can be programmed to achieve higher concurrency and provide better performance. The power consumption of the FPGA is lower than that of GPUs with the same workload. These reasons make the FPGA suitable for implementing the CNN release phase. They can provide relative output performance for GPUs and achieve low power consumption, which is very important for portable devices. To effectively implement the CNN output phase on the FPGA, the design should have high parallelism, and the hardware resources used should be minimized to reduce the area and power consumption. In the process of working with the help of a neural network, an algorithm for recognizing handwritten numbers is implemented. A special architecture is being created to implement a neural network at the appatent level. The performance during operation and power consumption is comparable to the performance of the processor and the GPU.