A Metric for Measuring Test Input Generation Effectiveness of Test Generation Methods for Boolean Expressions

2021 ◽  
Author(s):  
Deniz Kavzak Ufuktepe ◽  
Ekincan Ufuktepe ◽  
Tolga Ayav
Keyword(s):  
Test Generation ◽  
Test Input ◽  
Boolean Expressions

SXM-Based Web Test Generation with Respect to Logic Coverage Criteria

2017 ◽  
Vol 27 (04) ◽  
pp. 539-573
Author(s):  
Zhong Sheng Qian
Keyword(s):  
Shortest Path ◽  
Test Generation ◽  
Web Application ◽  
State Transition ◽  
Test Case ◽  
Test Cases ◽  
Transition Diagram ◽  
State Transition Diagram ◽  
Abstract Test Case ◽  
Boolean Expressions

This work proposes a Web test generation approach based on Stream X-Machines (SXMs). It employs relation matrix to construct test paths (abstract test cases). Two algorithms are presented, one for constructing the length-of-shortest-path matrix and another for establishing the shortest-path matrix from each state to other states in the state transition diagram of a SXM-based specification. For revealing the pre- and post-conditions of test paths conveniently, it transforms the execution of SXM-based abstract test cases into that of Boolean expressions and then tests the Web application under test by using those methods regarding Boolean expressions. Thus, an algorithm is designed to achieve test set for detecting logic connective fault. For a SXM-based abstract test case, the user operations involved are modeled by activity diagrams to derive practical test cases. An experiment on a miniature Web application is carried out to illustrate the SXM-based testing with respect to MC/DC, RC/DC, RMCC and GMCC coverage and in the meanwhile to compare these four criteria on their test effectiveness and fault-detecting ability.

scholarly journals How to Optimize the Use of SAT and SMT Solvers for Test Generation of Boolean Expressions

2015 ◽  
Vol 58 (11) ◽  
pp. 2900-2920 ◽  
Author(s):  
Paolo Arcaini ◽  
Angelo Gargantini ◽  
Elvinia Riccobene
Keyword(s):  
Test Generation ◽  
Smt Solvers ◽  
Boolean Expressions

Low Power and High Speed Sequential Circuits Test Architecture

2019 ◽  
Vol 12 ◽  
Author(s):  
Ahmed K. Jameil ◽  
Yasir Amer Abbas ◽  
Saad Al-Azawi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Test Generation ◽  
High Speed ◽  
Fir Filter ◽  
Sequential Circuits ◽  
Fir Filters ◽  
Design Verification ◽  
Sequential Circuit ◽  
Generation Algorithm

Background: The designed circuits are tested for faults detection in fabrication to determine which devices are defective. The design verification is performed to ensure that the circuit performs the required functions after manufacturing. Design verification is regarded as a test form in both sequential and combinational circuits. The analysis of sequential circuits test is more difficult than in the combinational circuit test. However, algorithms can be used to test any type of sequential circuit regardless of its composition. An important sequential circuit is the finite impulse response (FIR) filters that are widely used in digital signal processing applications. Objective: This paper presented a new design under test (DUT) algorithm for 4-and 8-tap FIR filters. Also, the FIR filter and the proposed DUT algorithm is implemented using field programmable gate arrays (FPGA). Method: The proposed test generation algorithm is implemented in VHDL using Xilinx ISE V14.5 design suite and verified by simulation. The test generation algorithm used FIR filtering redundant faults to obtain a set of target faults for DUT. The fault simulation is used in DUT to assess the benefit of test pattern in fault coverage. Results: The proposed technique provides average reductions of 20 % and 38.8 % in time delay with 57.39 % and 75 % reductions in power consumption and 28.89 % and 28.89 % slices reductions for 4- and 8-tap FIR filter, respectively compared to similar techniques. Conclusions: The results of implementation proved that a high speed and low power consumption design can be achieved. Further, the speed of the proposed architecture is faster than that of existing techniques.

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