Overhead and Performance Comparison of SET Fault Tolerant Circuits Used in Flash-based FPGAs

The aim of alternative fault tolerant techniques used in flash-based FPGAs, such as Single Event Transient (SET) filters, is to provide a resource savings advantage when compared to Triple Modular Redundancy (TMR). The purpose of this paper is to quantify, in terms of particular circuit characteristics, what the savings will be. The results suggest that the most important circuit characteristic to determine the gate count increase is the ratio of the number of primary outputs to the original circuit gate count, when considering a combinational circuit. When considering a sequential circuit, the most important circuit characteristic is the ratio of the number of Register Logic (RL) vs. Combinational Logic (CL) in the datapath. The theoretical study found that the DMR and delay element Guard Gate (GG) SET filter technique used in sequential circuits, proved more costly than TMR in terms of resource increase, when the ratio of the number of RL vs. CL is greater than 10% and 28% respectively. Chip-level synthesis of circuits using these filter techniques with one family of flash-based FPGAs shows no gate count cost benefit compared to TMR when the ratio of the number of RL vs. CL is greater than 13% and 15% respectively.

Design and Implementation of Sequential Circuit Based on Reversible Gate in Emerging Technologies for HCI

Affective computing is a growing research area used to develop the system in such a way to recognize, interpret, process and simulate the human emotions in a systematic manner. The main application of Affective computing is the human computer interaction, in which the communication between the human and the machine enhances by giving an appropriate response to the user in an effective and empathic manner. This paper mainly concentrates on the systems which can extract the previous, past and present information based on sequential circuit. Design sequential circuit (SC) with the help of reversible gate (RG) because RG is an emerging technology and consume low power and area. The SC is implemented Xilinx software and calculates parameters.

Low Power and High Speed Sequential Circuits Test Architecture

Background: The designed circuits are tested for faults detection in fabrication to determine which devices are defective. The design verification is performed to ensure that the circuit performs the required functions after manufacturing. Design verification is regarded as a test form in both sequential and combinational circuits. The analysis of sequential circuits test is more difficult than in the combinational circuit test. However, algorithms can be used to test any type of sequential circuit regardless of its composition. An important sequential circuit is the finite impulse response (FIR) filters that are widely used in digital signal processing applications. Objective: This paper presented a new design under test (DUT) algorithm for 4-and 8-tap FIR filters. Also, the FIR filter and the proposed DUT algorithm is implemented using field programmable gate arrays (FPGA). Method: The proposed test generation algorithm is implemented in VHDL using Xilinx ISE V14.5 design suite and verified by simulation. The test generation algorithm used FIR filtering redundant faults to obtain a set of target faults for DUT. The fault simulation is used in DUT to assess the benefit of test pattern in fault coverage. Results: The proposed technique provides average reductions of 20 % and 38.8 % in time delay with 57.39 % and 75 % reductions in power consumption and 28.89 % and 28.89 % slices reductions for 4- and 8-tap FIR filter, respectively compared to similar techniques. Conclusions: The results of implementation proved that a high speed and low power consumption design can be achieved. Further, the speed of the proposed architecture is faster than that of existing techniques.

Review of Clocked Storage Elements in Digital Circuit Design

Storage of digital circuit is "state" or memory. These are called sequential circuits. The most fundamental sequential circuit type that we will ponder is known as the Flip-Flop. It is ponder four distinct assortments of these gadgets and their utilization in registers and register documents, which can be considered as one type of on– CPU memory. The traditional memory, called RAM, is ordinarily not on the CPU chip. Regular Slam and its assortments, including RAM, ROM, SRAM, Measure, and SDRAM. True single-phase clock (TSPC) method of reasoning has found wide use in advanced plan. At first as a quick topology, the TSPC structure in like manner eats up less power and includes less areas than various systems. In flip-flop plan only a single transistor is being clocked by short heartbeat get ready which is known as True Single Phase Clocking (TSPC) flip-flop.