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On-Chip Bus Encoding for Power Minimization Under Delay Constraint
2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)
◽
10.1109/vdat.2007.373210
◽
2007
◽
Cited By ~ 3
Author(s):
Tzu-Wei Lin
◽
Shang-Wei Tu
◽
Jing-Yang Jou
Keyword(s):
Power Minimization
◽
Delay Constraint
◽
Bus Encoding
◽
On Chip
Download Full-text
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Partitioning Strategies of Wavelength-Routed Optical Networks-on-Chip for Laser Power Minimization
2015 Workshop on Exploiting Silicon Photonics for Energy-Efficient High Performance Computing
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10.1109/siphotonics.2015.13
◽
2015
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Author(s):
Marta Ortin
◽
Luca Ramini
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Marco Balboni
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Lorenzo Zuolo
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Keyword(s):
Optical Networks
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Laser Power
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Networks On Chip
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Power minimization for clustered routing in network on chip architectures
2015 2nd International Conference on Electronics and Communication Systems (ICECS)
◽
10.1109/ecs.2015.7124854
◽
2015
◽
Author(s):
T. Praveen Blessington
◽
B. Bhanu Murthy
◽
Fazal Noor Basha
Keyword(s):
Network On Chip
◽
Power Minimization
◽
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Delay and Power Minimization in VLSI Interconnects with Spatio-Temporal Bus-Encoding Scheme
IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07)
◽
10.1109/isvlsi.2007.35
◽
2007
◽
Cited By ~ 4
Author(s):
K S Sainarayanan
◽
C Raghunandan
◽
M B Srinivas
Keyword(s):
Power Minimization
◽
Encoding Scheme
◽
Vlsi Interconnects
◽
Bus Encoding
◽
Spatio Temporal
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Soft Error-Aware Voltage Scaling Technique for Power Minimization in Application-Specific Multiprocessor System-on-Chip
Journal of Low Power Electronics
◽
10.1166/jolpe.2009.1016
◽
2009
◽
Vol 5
(2)
◽
pp. 145-156
◽
Cited By ~ 7
Author(s):
Rishad Ahmed Shafik
◽
Bashir M. Al-Hashimi
◽
Sandip Kundu
◽
Alireza Ejlali
Keyword(s):
Voltage Scaling
◽
System On Chip
◽
Soft Error
◽
Multiprocessor System
◽
Power Minimization
◽
Scaling Technique
◽
On Chip
◽
Application Specific
Download Full-text
On-chip bus encoding for LC cross-talk reduction
2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT).
◽
10.1109/vdat.2005.1500063
◽
2005
◽
Cited By ~ 1
Author(s):
Jim-Sheng Huang
◽
Shang-Wei Tu
◽
Jing-Yang Jou
Keyword(s):
Cross Talk
◽
Bus Encoding
◽
On Chip
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Bus Encoding Technique Using Forbidden Transition Free Algorithm for Cross-Talk Reduction for On-chip VLSI Interconnect
2010 International Conference on Advances in Computer Engineering
◽
10.1109/ace.2010.17
◽
2010
◽
Cited By ~ 3
Author(s):
Souvik Sinha
◽
Rajib Kar
◽
A.K. Bhattacharjee
Keyword(s):
Cross Talk
◽
Forbidden Transition
◽
Bus Encoding
◽
On Chip
Download Full-text
Power minimization for clustered routing in network on chip architectures
2015 2nd International Conference on Electronics and Communication Systems (ICECS)
◽
10.1109/ecs.2015.7124866
◽
2015
◽
Author(s):
T. Praveen Blessington
◽
B. Bhanu Murthy
◽
Fazal Noor Basha
Keyword(s):
Network On Chip
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Power Minimization
◽
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Low power system on chip bus encoding scheme with crosstalk noise reduction capability
IEE Proceedings - Computers and Digital Techniques
◽
10.1049/ip-cdt:20050152
◽
2006
◽
Vol 153
(2)
◽
pp. 101
◽
Cited By ~ 29
Author(s):
Z. Khan
◽
T. Arslan
◽
A.T. Erdogan
Keyword(s):
Power System
◽
Low Power
◽
Noise Reduction
◽
System On Chip
◽
Crosstalk Noise
◽
Encoding Scheme
◽
Low Power System
◽
Bus Encoding
◽
On Chip
Download Full-text
Is more redundancy better for on-chip bus encoding
2006 IEEE International Conference on Acoustics Speed and Signal Processing Proceedings
◽
10.1109/iscas.2006.1693058
◽
2006
◽
Author(s):
Hsun-Chieh Yu
◽
Rung-Bin Lin
Keyword(s):
Bus Encoding
◽
On Chip
Download Full-text
RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
◽
10.1109/tcad.2005.860956
◽
2006
◽
Vol 25
(10)
◽
pp. 2258-2264
◽
Cited By ~ 34
Author(s):
S.-W. Tu
◽
Y.-W. Chang
◽
J.-Y. Jou
Keyword(s):
Delay Reduction
◽
Bus Encoding
◽
On Chip
Download Full-text
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