RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2005.860956 ◽

2006 ◽

Vol 25 (10) ◽

pp. 2258-2264 ◽

Author(s):

S.-W. Tu ◽

Y.-W. Chang ◽

J.-Y. Jou

Keyword(s):

Delay Reduction ◽

Bus Encoding ◽

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Temporal Redundancy Based Encoding Technique for Peak Power and Delay Reduction of On-Chip Buses

Journal of Low Power Electronics ◽

10.1166/jolpe.2006.099 ◽

2006 ◽

Vol 2 (3) ◽

pp. 425-436

Author(s):

K. Najeeb ◽

Vishal Gupta ◽

V. Kamakoti ◽

Madhu Mutyam

Keyword(s):

Delay Reduction ◽

On Chip ◽

Temporal Redundancy

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On-chip bus encoding for LC cross-talk reduction

2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT). ◽

10.1109/vdat.2005.1500063 ◽

2005 ◽

Author(s):

Jim-Sheng Huang ◽

Shang-Wei Tu ◽

Jing-Yang Jou

Keyword(s):

Bus Encoding ◽

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On-Chip Bus Encoding for Power Minimization Under Delay Constraint

2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) ◽

10.1109/vdat.2007.373210 ◽

2007 ◽

Author(s):

Tzu-Wei Lin ◽

Shang-Wei Tu ◽

Jing-Yang Jou

Keyword(s):

Power Minimization ◽

Delay Constraint ◽

Bus Encoding ◽

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Burst Error Detection Hybrid ARQ with Crosstalk-Delay Reduction for Reliable On-chip Interconnects

2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems ◽

10.1109/dft.2009.45 ◽

2009 ◽

Author(s):

Bo Fu ◽

Paul Ampadu

Keyword(s):

Error Detection ◽

Delay Reduction ◽

Burst Error ◽

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Bus Encoding Technique Using Forbidden Transition Free Algorithm for Cross-Talk Reduction for On-chip VLSI Interconnect

2010 International Conference on Advances in Computer Engineering ◽

10.1109/ace.2010.17 ◽

2010 ◽

Author(s):

Souvik Sinha ◽

Rajib Kar ◽

A.K. Bhattacharjee

Keyword(s):

Forbidden Transition ◽

Bus Encoding ◽

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Low power system on chip bus encoding scheme with crosstalk noise reduction capability

IEE Proceedings - Computers and Digital Techniques ◽

10.1049/ip-cdt:20050152 ◽

2006 ◽

Vol 153 (2) ◽

pp. 101 ◽

Author(s):

Z. Khan ◽

T. Arslan ◽

A.T. Erdogan

Keyword(s):

Power System ◽

Low Power ◽

Noise Reduction ◽

System On Chip ◽

Crosstalk Noise ◽

Encoding Scheme ◽

Low Power System ◽

Bus Encoding ◽

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Is more redundancy better for on-chip bus encoding

2006 IEEE International Conference on Acoustics Speed and Signal Processing Proceedings ◽

10.1109/iscas.2006.1693058 ◽

2006 ◽

Author(s):

Hsun-Chieh Yu ◽

Rung-Bin Lin

Keyword(s):

Bus Encoding ◽

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RLC Coupling-Aware Simulation for On-Chip Buses and their Encoding for Delay Reduction

2005 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.2005.1465541 ◽

2005 ◽

Author(s):

Shang-Wei Tu ◽

Jing-Yang Jou ◽

Yao-Wen Chang

Keyword(s):

Delay Reduction ◽

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Wire Optimization and Delay Reduction for High-Performance on-Chip Interconnection in GALS Systems

ETRI Journal ◽

10.4218/etrij.17.0116.0052 ◽

2017 ◽

Vol 39 (4) ◽

pp. 582-591 ◽

Author(s):

Myeong-Hoon Oh ◽

Young Woo Kim ◽

Hag Young Kim ◽

Young-Kyun Kim ◽

Jin-Sung Kim

Keyword(s):

High Performance ◽

Delay Reduction ◽

On Chip ◽

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Optimization of Delay and Energy in On-Chip Buses using Bus Encoding Technique

International Journal of Computer Applications ◽

10.5120/15035-3376 ◽

2014 ◽

Vol 86 (12) ◽

pp. 7-12

Author(s):

Souvik Singha ◽

G. K. Mahanti

Keyword(s):

Bus Encoding ◽

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