Michelson interferometer-based interleaver design algorithm based on IIR filter model

In this paper, we present a numerical method for the equiripple approximation of Impulse Infinite Response digital filters. The proposed method is based on the formulation of a generalized eigenvalue problem by using Rational Remez Exchange algorithm. In this paper, conventional Remez algorithm is modified to get the ratio of weights in the different bands exactly. In Rational Remez, squared magnitude response of the IIR filter is approximated in the Chebyshev sense by solving for an eigenvalue problem, in which real maximum eigenvalue is chosen and corresponding to that eigenvectors are found, and from that optimal filter coefficients are obtained through few iterations with controlling the ratio of ripples.Â The design algorithm is computationally efficient because it not only retains the speed inherent in the Remez exchange algorithm but also simplifies the interpolation step.

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Performance Investigation of Digital Lowpass IIR Filter Based on Different Platforms

International journal of electrical and computer engineering systems ◽

10.32985/ijeces.12.2.5 ◽

2021 ◽

Vol 12 (2) ◽

pp. 105-111

Author(s):

Raaed Faleh Hassan

Keyword(s):

Integrated Circuit ◽

High Speed ◽

Filter Design ◽

Basic Unit ◽

Infinite Impulse Response ◽

Design Algorithm ◽

System Generator ◽

Iir Filter ◽

Hardware Description ◽

And Performance

The work presented in this paper illuminates the design and simulation of a recursive or Infinite Impulse Response (IIR) filter. The proposed design algorithm employs the Genetic Algorithm to determine the filter coefficients to satisfy the required performance. The effectiveness of different platforms on filter design and performance has been studied in this paper. Three different platforms are considered to implement and verify the designed filter’s work through simulation. The first platform is the MATLAB/SIMULINK software package used to implement the Biquad form filter. This technique is the basis for the software implementation of the designed IIR filter. The HDL – Cosimulation technique is considered the second one; it inspired to take advantage of the existing tools in SIMULINK to convert the designed filter algorithm to the Very high-speed integrated circuit Hardware Description Language (VHDL) format. The System Generator is employed as the third technique, in which the designed filter is implemented as a hardware structure based on basic unit blocks provided by Xilinx System Generator. This technique facilitates the implementation of the designed filter in the FPGA target device. Simulation results show that the performance of the designed filter is remarkably reliable even with severe noise levels.

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