New artificial neural network design for Chua chaotic system prediction using FPGA hardware co-simulation

<p>This study aims to design a new architecture of the artificial neural networks (ANNs) using the Xilinx system generator (XSG) and its hardware co-simulation equivalent model using field programmable gate array (FPGA) to predict the behavior of Chua’s chaotic system and use it in hiding information. The work proposed consists of two main sections. In the first section, MATLAB R2016a was used to build a 3×4×3 feed forward neural network (FFNN). The training results demonstrate that FFNN training in the Bayesian regulation algorithm is sufficiently accurate to directly implement. The second section demonstrates the hardware implementation of the network with the XSG on the Xilinx artix7 xc7a100t-1csg324 chip. Finally, the message was first encrypted using a dynamic Chua system and then decrypted using ANN’s chaotic dynamics. ANN models were developed to implement hardware in the FPGA system using the IEEE 754 Single precision floating-point format. The ANN design method illustrated can be extended to other chaotic systems in general.</p>

FPGA Implementation of Eye Movement Detection Algorithm

In this paper, we propose an simple and efficient VLSI hardware architecture is implemented for eye movement detection. For Eye movement detection reading activity Electrooculography (EOG) signal is considered. Here, for denoising the noisy EOG signal efficient FIR filter and for decomposition of denoised EOG signal an efficient Haar wavelet transform architecture is used respectively. The modified VLSI hardware architecture method detected the saccade (left movement of eye and right movement of eye) and blink efficiently. The hardware architecture of the eye movement detection algorithm functionality is verified by using Xilinx System Generator hardware co-simulation tool. The eye movement detection algorithm is implemented on the ZedBoard FPGA using Xilinx Vivado design suite.

SOFTWARE-DEFINED RADAR TARGET SIMULATOR WITH DRFM FOR AUTOMATED RADARS TESTING

The paper describes a software-defined radar target simulator with DRFM. One may use such a device to test radars under development and evaluate their reliability in environments with radio frequency interference. The paper describes in detail a general algorithm of the target simulation and its modules for the simulation of range and speed. The authors also implemented the frequency shift module for the simulator in Xilinx System Generator and wrote this module in VHDL. One may find in the paper a comparison of the FPGA resources required for such implementations.

IoT Based Image Processing Filters

Internet of things (IoT) becomes the backbone of the advanced countries and it has a real contribute to exchange the traditional style or way of practical life, even personal life into smart style, with (IoT) technology the life become more and more easy and professional. internet of things achieves various applications coordinate with sensors and standard protocols to apply what is called machine -to- machine connection (M2M), in this paper we will talk more about the concept of (M2M), the main component of internet of things and finally the common protocols that is used in network, in addition to that this work present an IOT operation with processing system using camera for capturing image and Xilinx system generator(XSG)models for designing image processing algorithms and the result of the processing is an image with black and white for edge detection and Thresholding models and gray color image for gray enhancement model.

IoT Based Image Processing Filters

Internet of things (IoT) becomes the backbone of the advanced countries and it has a real contribute to exchange the traditional style or way of practical life, even personal life into smart style, with (IoT) technology the life become more and more easy and professional. internet of things achieves various applications coordinate with sensors and standard protocols to apply what is called machine -to- machine connection (M2M), in this paper we will talk more about the concept of (M2M), the main component of internet of things and finally the common protocols that is used in network, in addition to that this work present an IOT operation with processing system using camera for capturing image and Xilinx system generator(XSG)models for designing image processing algorithms and the result of the processing is an image with black and white for edge detection and Thresholding models and gray color image for gray enhancement model.

A Guide on Using Xilinx System Generator to Design and Implement Real-Time Audio Effects on FPGA

The enormous progress in communication technology has led to a tremendous need to provide an ideal environment for the transmission, storing, and processing of digital multimedia content, where the audio signal takes the lion's share of it. Audio processing covers many diverse fields, its main aim is presenting sound to human listeners. Recently, digital audio processing became an active research area, it covers everything from theory to practice in relation to transmission, compression, filtering, and adding special effects to an audio signal. The aim of this work is to present the real-time implementation steps of some audio effects namely, the echo and Flanger effects on Field Programmable Gate Array (FPGA). Today, FPGAs are the best choice in data processing because they provide more flexibility, performance, and huge processing capabilities with great power efficiency. Designs are achieved using the XSG tool (Xilinx System Generator), which makes complex designs easier without prior knowledge of hardware description languages. The paper is presented as a guide with deep technical details about designing and real-time implementation steps. We decided to transfer some experience to designers who want to rapidly prototype their ideas using tools such as XSG. All the designs have been simulated and verified under Simulink/Matlab environment, then exported to Xilinx ISE (Integrated Synthesis Environment) tool for the rest of the implementation steps. The paper also gives an idea of interfacing the FPGA with the LM4550 AC’97 codec using VHDL coding. The ATLYS development board based on Xilinx Spartan-6 LX45 FPGA is used for the real-time implementation.