scholarly journals Performance Investigation of Digital Lowpass IIR Filter Based on Different Platforms

2021 ◽  
Vol 12 (2) ◽  
pp. 105-111
Author(s):  
Raaed Faleh Hassan
Keyword(s):  
Integrated Circuit ◽  
High Speed ◽  
Filter Design ◽  
Basic Unit ◽  
Infinite Impulse Response ◽  
Design Algorithm ◽  
System Generator ◽  
Iir Filter ◽  
Hardware Description ◽  
And Performance

The work presented in this paper illuminates the design and simulation of a recursive or Infinite Impulse Response (IIR) filter. The proposed design algorithm employs the Genetic Algorithm to determine the filter coefficients to satisfy the required performance. The effectiveness of different platforms on filter design and performance has been studied in this paper. Three different platforms are considered to implement and verify the designed filter’s work through simulation. The first platform is the MATLAB/SIMULINK software package used to implement the Biquad form filter. This technique is the basis for the software implementation of the designed IIR filter. The HDL – Cosimulation technique is considered the second one; it inspired to take advantage of the existing tools in SIMULINK to convert the designed filter algorithm to the Very high-speed integrated circuit Hardware Description Language (VHDL) format. The System Generator is employed as the third technique, in which the designed filter is implemented as a hardware structure based on basic unit blocks provided by Xilinx System Generator. This technique facilitates the implementation of the designed filter in the FPGA target device. Simulation results show that the performance of the designed filter is remarkably reliable even with severe noise levels.

Design and Performance Analysis of Application Specific Integrated Circuit for Internet of Things Applications

2020 ◽  
Vol 18 (9) ◽  
pp. 700-705
Author(s):  
Vivek Pogra ◽  
Amandeep Singh ◽  
Santosh Kumar Vishvakarma ◽  
Balwinder Raj
Keyword(s):  
Internet Of Things ◽  
Integrated Circuit ◽  
High Speed ◽  
Direct Memory Access ◽  
Electronic Systems ◽  
Application Specific Integrated Circuit ◽  
Hardware Description ◽  
And Performance ◽  
Application Specific ◽  
Novel Design

This paper proposes a novel design of application specific integrated circuit (ASIC) which is capable of connecting sensor network and other electronic systems to the internet. The transfer of data between different networks and electronic systems is controlled by internet of things (IoT) platform with the help of instruction sent to ASIC. ASIC will act as serial peripheral interface (SPI) master to all connected networks and data will be transferred serially between them. The different ASIC modules are SPI module, control module, memory module and data/instruction decoder with additional modules built-in self-test (BIST) and direct memory access (DMA). The proposed ASIC will consume less power as compared to conventional microcontroller/microprocessor due to SPI feature along with DMA on ASIC for IoT applications. It is described in very high speed integrated circuit hardware description language (VHDL) at register transfer level (RTL) and simulation is done on the Vivado 2016.2.

scholarly journals Implementation of Word Level Parallel Processing Unfolding Algorithm using VHDL

2019 ◽  
Vol 8 (6) ◽  
pp. 664-667
Keyword(s):  
Parallel Processing ◽  
Impulse Response ◽  
Integrated Circuit ◽  
High Speed ◽  
Finite Impulse Response ◽  
Critical Path ◽  
Experimental Result ◽  
Infinite Impulse Response ◽  
Path Delay ◽  
Iir Filter

Aim of this paper is to apply the unfolding algorithm to FIR (Finite Impulse Response) and IIR (Infinite Impulse Response) filter and compare with original filter and parallel processing filters architecture. FIR filter and IIR filter are implemented by using VHDL (Very High Speed Integrated Circuit Hardware Description Language).In this paper, 2-parallel processing and 3-parallel processing of FIR and IIR filter are implemented and FIR and IIR filter are also implemented with unfolding factor 2 and unfolding factor 3 using VHDL. The simulation is done on Artix-7 series FPGA, target device (xc7a200tfbg676) (speed grade -1) using VIVADO 2016.3. Implemented design works on 1200 KHz clock whereas parallel inputs are generated on 3600 KHz clock. The proposed technique reduces the critical path delay in comparison with existing literature. Also, the experimental result shows that the speed for 3-unfolded IIR filter is more than 3-parallel IIR filter

scholarly journals SYNTHESIS AND FPGA–IMPLEMENTATION BASED NEURAL TECHNIQUE OF A NONLINEAR ADC MODEL

2014 ◽  
pp. 27-33
Author(s):  
Mounir Bouhedda ◽  
Mokhtar Attari
Keyword(s):  
Integrated Circuit ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Hardware Description Language ◽  
Description Language ◽  
Analog To Digital ◽  
Field Programmable ◽  
Hardware Description ◽  
Nonlinear Analog ◽  
Very High

The aim of this paper is to introduce a new architecture using Artificial Neural Networks (ANN) in designing a 6-bit nonlinear Analog to Digital Converter (ADC). A study was conducted to synthesise an optimal ANN in view to FPGA (Field Programmable Gate Array) implementation using Very High-speed Integrated Circuit Hardware Description Language (VHDL). Simulation and tests results are carried out to show the efficiency of the designed ANN.

A modeling method of algorithm-hardware based on SysML

2021 ◽  
Author(s):  
Liu Yue ◽  
Zhao Chun ◽  
Zhang Lin
Keyword(s):  
Graphical Models ◽  
Integrated Circuit ◽  
High Speed ◽  
System Modeling ◽  
Modeling Method ◽  
Description Language ◽  
Hardware Description ◽  
Circuit And System ◽  
Graphical System ◽  
Hardware Circuit

In the process of complex product design, modeling in different fields and different disciplines is often involved. Designers often face many different development kits, platforms, and theories, among which significant differences exist. Especially in the process of algorithm-hardware implementation, it is necessary to have mastery of the knowledge including algorithm, hardware, circuit, and system engineering. In this paper, a modeling method of algorithm-hardware based on SysML is proposed to reduce the difficulty of algorithm-hardware modeling. By using the method, the designers who do not know the knowledge of hardware can also easily build the algorithm-hardware model. In this method, a method of graphical system modeling based on SysML is used, where the elements of the algorithm-hardware model are described by SysML graphical models. Then, the SysML graphical models are converted to Very-High-Speed Integrated Circuit Hardware Description Language. At last, a detecting algorithm of random number is complemented by the modeling method in this paper and the simulation results are presented at the conclusion.

scholarly journals Comparison of Circular Symmetric Low-Pass Digital IIR Filter Design Using Evolutionary Computation Techniques

Mathematics ◽  
2020 ◽  
Vol 8 (8) ◽  
pp. 1226 ◽  
Author(s):  
Omar Avalos ◽  
Erik Cuevas ◽  
Jorge Gálvez ◽  
Essam H. Houssein ◽  
Kashif Hussain
Keyword(s):  
Evolutionary Computation ◽  
Transfer Functions ◽  
Filter Design ◽  
Statistical Treatment ◽  
Optimization Methods ◽  
Intelligence Community ◽  
Infinite Impulse Response ◽  
Iir Filters ◽  
Iir Filter ◽  
Wide Range

The design of two-dimensional Infinite Impulse Response (2D-IIR) filters has recently attracted attention in several areas of engineering because of their wide range of applications. Synthesizing a user-defined filter in a 2D-IIR structure can be interpreted as an optimization problem. However, since 2D-IIR filters can easily produce unstable transfer functions, they tend to compose multimodal error surfaces, which are computationally difficult to optimize. On the other hand, Evolutionary Computation (EC) algorithms are well-known global optimization methods with the capacity to explore complex search spaces for a suitable solution. Every EC technique holds distinctive attributes to properly satisfy particular requirements of specific problems. Hence, a particular EC algorithm is not able to solve all problems adequately. To determine the advantages and flaws of EC techniques, their correct evaluation is a critical task in the computational intelligence community. Furthermore, EC algorithms are stochastic processes with random operations. Under such conditions, for obtaining significant conclusions, appropriate statistical methods must be considered. Although several comparisons among EC methods have been reported in the literature, their conclusions are based on a set of synthetic functions, without considering the context of the problem or appropriate statistical treatment. This paper presents a comparative study of various EC techniques currently in use employed for designing 2D-IIR digital filters. The results of several experiments are presented and statistically analyzed.

scholarly journals High Throughput Implementation of the Keccak Hash Function Using the Nios-II Processor

Technologies ◽  
2020 ◽  
Vol 8 (1) ◽  
pp. 15
Author(s):  
Argyrios Sideris ◽  
Theodora Sanida ◽  
Minas Dasygenis
Keyword(s):  
Integrated Circuit ◽  
Hash Function ◽  
High Speed ◽  
Critical Role ◽  
Optimization Techniques ◽  
Floating Point ◽  
Throughput Optimization ◽  
Nios Ii ◽  
Hash Algorithm ◽  
Hardware Description

Presently, cryptographic hash functions play a critical role in many applications, such as digital signature systems, security communications, protocols, and network security infrastructures. The new standard cryptographic hash function is Secure Hash Algorithm 3 (SHA-3), which is not vulnerable to attacks. The Keccak algorithm is the winner of the NIST competition for the adoption of the new standard SHA-3 hash algorithm. In this work, we present hardware throughput optimization techniques for the SHA-3 algorithm using the Very High Speed Integrated Circuit Hardware Description Language (VHDL) programming language for all output lengths in the Keccak hash function (224, 256, 384 and 512). Our experiments were performed with the Nios II processor on the FPGA Arria 10 GX (10AX115N2P45E1SG). We applied two architectures, one without custom instruction and one with floating point hardware 2. Finally, we compare the results with other existing similar designs and found that the proposed design with floating point 2 optimizes throughput (Gbps) compared to existing FPGA implementations.

scholarly journals IIR Filter Design Using African Buffalo Optimization

2020 ◽  
pp. 95-99
Author(s):  
Jaishankar B ◽  
Govindaraj V ◽  
Sri kanth
Keyword(s):  
Signal Processing ◽  
Filter Design ◽  
Search Algorithm ◽  
Phase Error ◽  
Signal Amplitude ◽  
Performance Outcomes ◽  
Infinite Impulse Response ◽  
Modern World ◽  
African Buffalo ◽  
Iir Filter

In the modern world, the digital signal processing embeds more in real time applications. Several researchers focused on filtering process to identify the limitation in traditional methods. In this article, the meta-heuristic algorithm is deployed for optimizing infinite impulse response (IIR) filter design. The traditional IIR filter results create computational complexity and its performance is worse in the case of a noisy environment. In signal processing, IIR plays several roles in filtering and monitoring the signal amplitude. The African Buffalo Optimization (ABO) is quite easy for implementation and its performance outcomes solved many problems in various domains. Hence, it is selected for solving IIR filter problems for obtaining optimal filter coefficients. Initially, IIR filter is designed for different orders under ABO concept. The ABO based IIR filter’s performance is superior to those obtained by Genetic Algorithm and cuckoo search algorithm. The proposed method’s performance result proves that it has a smaller magnitude error and phase error with fast convergence rate.

scholarly journals Meta-heuristic techniques for optimal design of analog and digital filter

2020 ◽  
Vol 19 (2) ◽  
pp. 669
Author(s):  
El Beqal Asmae ◽  
Kritele Loubna ◽  
Benhala Bachir ◽  
Zorkani Izeddine
Keyword(s):  
Optimal Design ◽  
Filter Design ◽  
Analog Filters ◽  
Infinite Impulse Response ◽  
Band Pass Filter ◽  
Pass Filter ◽  
Iir Filter ◽  
Design Error ◽  
Heuristic Techniques ◽  
Band Pass

In this paper, two Meta-heuristic techniques; namely Ant Colony Optimization (ACO) and Genetic Algorithm (GA) have been applied for the optimal design of digital and analog filters. Those techniques have been used to solve multimodal optimization problem in Infinite Impulse Response (IIR) filter design and to select the optimal component values from industrial series as well as to minimize the total design error of a 2nd order Sallen-Key active band-pass filter, also a comparison between the performances reached by those two Meta-heuristics was made in this article.

Digital Stable IIR Band Pass Filter Design Using Seeker Optimization Technique

2014 ◽  
Vol 905 ◽  
pp. 406-410 ◽  
Author(s):  
S.K. Saha ◽  
Rajib Kar ◽  
D. Mandal ◽  
S.P. Ghoshal
Keyword(s):  
Filter Design ◽  
Fitness Function ◽  
Stop Band ◽  
Infinite Impulse Response ◽  
Pass Band ◽  
Band Pass Filter ◽  
Pass Filter ◽  
Iir Filter ◽  
Real Coded Genetic Algorithm ◽  
Band Pass

This paper presents a novel, control parameter independent evolutionary search technique known as Seeker Optimization Algorithm (SOA) for the design of a eighth order Infinite Impulse Response (IIR) Band Pass (BP) filter. A new fitness function has also been adopted in this paper to improve the stop band attenuation to a great extent. The performance of the SOA based IIR BP filter design has proven to be much superior as compared to those obtained by real coded genetic algorithm (RGA) and standard particle swarm optimization (PSO) in terms of highest sharpness at cut-off, smallest pass band ripple, highest stop band attenuation, smallest stop band ripple and also the fastest convergence speed with assured stability recognized by the pole-zero analysis of the designed optimized IIR filter.

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