Adapting the minimum variance beamformer to a graphics processing unit for active sonar imaging systems

2013 ◽  
Vol 133 (5) ◽  
pp. 3613-3613 ◽  
Author(s):  
Jo Inge Buskenes ◽  
Jon Petter Åsen ◽  
Carl-Inge C. Nilsen ◽  
Andreas Austeng
Keyword(s):  
Graphics Processing Unit ◽  
Minimum Variance ◽  
Imaging Systems ◽  
Processing Unit ◽  
Active Sonar ◽  
Sonar Imaging ◽  
Graphics Processing

Fast iterative solvers for large compressed-sparse row linear systems on graphics processing unit

2015 ◽  
Vol 10 (1) ◽  
pp. 3-18 ◽  
Author(s):  
Frédéric Magoulès ◽  
Abal-Kassim Cheik Ahamed ◽  
Roman Putanowicz
Keyword(s):  
Linear Systems ◽  
Graphics Processing Unit ◽  
Iterative Solvers ◽  
Processing Unit ◽  
Compressed Sparse Row ◽  
Graphics Processing

Implementing wide baseline matching algorithms on a graphics processing unit.

2007 ◽  
Author(s):  
Fredrick H. Rothganger ◽  
Kurt W. Larson ◽  
Antonio Ignacio Gonzales ◽  
Daniel S. Myers
Keyword(s):  
Graphics Processing Unit ◽  
Processing Unit ◽  
Wide Baseline Matching ◽  
Graphics Processing

scholarly journals Two Decades of 4D-QSAR: A Dying Art or Staging a Comeback?

2021 ◽  
Vol 22 (10) ◽  
pp. 5212
Author(s):  
Andrzej Bak
Keyword(s):  
Molecular Conformation ◽  
Graphics Processing Unit ◽  
Processing Unit ◽  
Diverse Range ◽  
Current State ◽  
Gpu Clusters ◽  
Pharmacophore Hypothesis ◽  
Rising Power ◽  
Graphics Processing ◽  
Ligand Conformation

A key question confronting computational chemists concerns the preferable ligand geometry that fits complementarily into the receptor pocket. Typically, the postulated ‘bioactive’ 3D ligand conformation is constructed as a ‘sophisticated guess’ (unnecessarily geometry-optimized) mirroring the pharmacophore hypothesis—sometimes based on an erroneous prerequisite. Hence, 4D-QSAR scheme and its ‘dialects’ have been practically implemented as higher level of model abstraction that allows the examination of the multiple molecular conformation, orientation and protonation representation, respectively. Nearly a quarter of a century has passed since the eminent work of Hopfinger appeared on the stage; therefore the natural question occurs whether 4D-QSAR approach is still appealing to the scientific community? With no intention to be comprehensive, a review of the current state of art in the field of receptor-independent (RI) and receptor-dependent (RD) 4D-QSAR methodology is provided with a brief examination of the ‘mainstream’ algorithms. In fact, a myriad of 4D-QSAR methods have been implemented and applied practically for a diverse range of molecules. It seems that, 4D-QSAR approach has been experiencing a promising renaissance of interests that might be fuelled by the rising power of the graphics processing unit (GPU) clusters applied to full-atom MD-based simulations of the protein-ligand complexes.

Parallelization of Global Sequence Alignment on Graphics Processing Unit

2020 ◽  
Author(s):  
Kailash W. Kalare ◽  
Mohammad S. Obaidat ◽  
Jitendra V. Tembhurne ◽  
Chandrashekhar Meshram ◽  
Kuei-Fang Hsiao
Keyword(s):  
Sequence Alignment ◽  
Graphics Processing Unit ◽  
Processing Unit ◽  
Graphics Processing

Real-time, High-resolution Depth Upsampling on Embedded Accelerators

2021 ◽  
Vol 20 (3) ◽  
pp. 1-22
Author(s):  
David Langerman ◽  
Alan George
Keyword(s):  
High Resolution ◽  
Low Power ◽  
Real Time ◽  
Mixed Reality ◽  
Graphics Processing Unit ◽  
Processing Unit ◽  
Reconfigurable Logic ◽  
Depth Sensors ◽  
Time Requirements ◽  
Graphics Processing

High-resolution, low-latency apps in computer vision are ubiquitous in today’s world of mixed-reality devices. These innovations provide a platform that can leverage the improving technology of depth sensors and embedded accelerators to enable higher-resolution, lower-latency processing for 3D scenes using depth-upsampling algorithms. This research demonstrates that filter-based upsampling algorithms are feasible for mixed-reality apps using low-power hardware accelerators. The authors parallelized and evaluated a depth-upsampling algorithm on two different devices: a reconfigurable-logic FPGA embedded within a low-power SoC; and a fixed-logic embedded graphics processing unit. We demonstrate that both accelerators can meet the real-time requirements of 11 ms latency for mixed-reality apps. 1

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