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NON-SEQUENTIAL INSTRUCTION CACHE PREFETCHING FOR MULTIPLE–ISSUE PROCESSORS
International Journal of High Speed Computing
◽
10.1142/s0129053399000065
◽
1999
◽
Vol 10
(01)
◽
pp. 115-140
◽
Cited By ~ 6
Author(s):
ALEXANDER V. VEIDENBAUM
◽
QINGBO ZHAO
◽
ABDUHL SHAMEER
Keyword(s):
Instruction Cache
◽
Sequential Instruction
Download Full-text
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Filtering drowsy instruction cache to achieve better efficiency
Proceedings of the 2008 ACM symposium on Applied computing - SAC '08
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10.1145/1363686.1364050
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2008
◽
Author(s):
Roberto Giorgi
◽
Paolo Bennati
Keyword(s):
Instruction Cache
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Evaluating instruction cache vulnerability to transient errors
Proceedings of the 2005 workshop on MEmory performance DEaling with Applications, systems and architectures - MEDEA '06
◽
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◽
2006
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Keyword(s):
Instruction Cache
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Transient Errors
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A case for shared instruction cache on chip multiprocessors running OLTP
ACM SIGARCH Computer Architecture News
◽
10.1145/1024295.1024297
◽
2004
◽
Vol 32
(3)
◽
pp. 11-18
◽
Cited By ~ 3
Author(s):
Partha Kundu
◽
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◽
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◽
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Keyword(s):
Chip Multiprocessors
◽
Instruction Cache
◽
On Chip
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Evaluating instruction cache vulnerability to transient errors
ACM SIGARCH Computer Architecture News
◽
10.1145/1327312.1327317
◽
2007
◽
Vol 35
(4)
◽
pp. 21-28
◽
Cited By ~ 6
Author(s):
Jun Yan
◽
Wei Zhang
Keyword(s):
Instruction Cache
◽
Transient Errors
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Ripple: Profile-Guided Instruction Cache Replacement for Data Center Applications
2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA)
◽
10.1109/isca52012.2021.00063
◽
2021
◽
Author(s):
Tanvir Ahmed Khan
◽
Dexin Zhang
◽
Akshitha Sriraman
◽
Joseph Devietti
◽
Gilles Pokam
◽
...
Keyword(s):
Data Center
◽
Cache Replacement
◽
Instruction Cache
◽
Guided Instruction
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Software-Level Instruction-Cache Leakage Reduction Using Value-Dependence of SRAM Leakage in Nanometer Technologies
Transactions on High-Performance Embedded Architectures and Compilers III - Lecture Notes in Computer Science
◽
10.1007/978-3-642-19448-1_15
◽
2011
◽
pp. 275-299
Author(s):
Maziar Goudarzi
◽
Tohru Ishihara
◽
Hamid Noori
Keyword(s):
Instruction Cache
◽
Leakage Reduction
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Design Methodology and Software Tool for Estimation of Multi-level Instruction Cache Memory Miss Rate
Lecture Notes in Computer Science - Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
◽
10.1007/978-3-540-74442-9_49
◽
2007
◽
pp. 505-515
Author(s):
N. Kroupis
◽
D. Soudris
Keyword(s):
Design Methodology
◽
Software Tool
◽
Cache Memory
◽
Instruction Cache
◽
Multi Level
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Power Reduction of a Set-Associative Instruction Cache Using a Dynamic Early Tag Lookup
10.23919/date51398.2021.9474191
◽
2021
◽
Author(s):
Chun-Chang Yu
◽
Yu Hen Hu
◽
Yi-Chang Lu
◽
Charlie Chung-Ping Chen
Keyword(s):
Power Reduction
◽
Instruction Cache
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Performance Estimation of Embedded Software with Instruction Cache Modeling
Readings in Hardware/Software Co-Design
◽
10.1016/b978-155860702-6/50015-6
◽
2002
◽
pp. 167-178
◽
Cited By ~ 1
Author(s):
YAU-TSUN STEVEN LI
◽
SHARAD MALIK
◽
ANDREW WOLFE
Keyword(s):
Embedded Software
◽
Performance Estimation
◽
Instruction Cache
◽
Cache Modeling
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An Innovative Instruction Cache for Embedded Processors
Advances in Computer Systems Architecture - Lecture Notes in Computer Science
◽
10.1007/11572961_5
◽
2005
◽
pp. 41-51
Author(s):
Cheol Hong Kim
◽
Sung Woo Chung
◽
Chu Shik Jhon
Keyword(s):
Embedded Processors
◽
Instruction Cache
◽
Innovative Instruction
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