Evaluating instruction cache vulnerability to transient errors

ACM SIGARCH Computer Architecture News ◽

10.1145/1327312.1327317 ◽

2007 ◽

Vol 35 (4) ◽

pp. 21-28 ◽

Author(s):

Jun Yan ◽

Wei Zhang

Keyword(s):

Instruction Cache ◽

Transient Errors

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Evaluating instruction cache vulnerability to transient errors

Proceedings of the 2005 workshop on MEmory performance DEaling with Applications, systems and architectures - MEDEA '06 ◽

10.1145/1166133.1166136 ◽

2006 ◽

Author(s):

Jun Yan ◽

Wei Zhang

Keyword(s):

Instruction Cache ◽

Transient Errors

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Filtering drowsy instruction cache to achieve better efficiency

Proceedings of the 2008 ACM symposium on Applied computing - SAC '08 ◽

10.1145/1363686.1364050 ◽

2008 ◽

Author(s):

Roberto Giorgi ◽

Paolo Bennati

Keyword(s):

Instruction Cache

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An Area-Efficient Approach to Improving Register File Reliability against Transient Errors

21st International Conference on Advanced Information Networking and Applications Workshops (AINAW'07) ◽

10.1109/ainaw.2007.78 ◽

2007 ◽

Author(s):

Mallik Kandala ◽

Wei Zhang ◽

Laurence T. Yang

Keyword(s):

Register File ◽

Efficient Approach ◽

Transient Errors ◽

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A case for shared instruction cache on chip multiprocessors running OLTP

ACM SIGARCH Computer Architecture News ◽

10.1145/1024295.1024297 ◽

2004 ◽

Vol 32 (3) ◽

pp. 11-18 ◽

Author(s):

Partha Kundu ◽

Murali Annavaram ◽

Trung Diep ◽

John Shen

Keyword(s):

Chip Multiprocessors ◽

Instruction Cache ◽

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Lost in transcription: transient errors in information transfer

Current Opinion in Microbiology ◽

10.1016/j.mib.2015.01.010 ◽

2015 ◽

Vol 24 ◽

pp. 80-87 ◽

Author(s):

Alasdair JE Gordon ◽

Dominik Satory ◽

Jennifer A Halliday ◽

Christophe Herman

Keyword(s):

Information Transfer ◽

Transient Errors

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Ripple: Profile-Guided Instruction Cache Replacement for Data Center Applications

2021 ACM/IEEE 48th Annual International Symposium on Computer Architecture (ISCA) ◽

10.1109/isca52012.2021.00063 ◽

2021 ◽

Author(s):

Tanvir Ahmed Khan ◽

Dexin Zhang ◽

Akshitha Sriraman ◽

Joseph Devietti ◽

Gilles Pokam ◽

...

Keyword(s):

Data Center ◽

Cache Replacement ◽

Instruction Cache ◽

Guided Instruction

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Software-Level Instruction-Cache Leakage Reduction Using Value-Dependence of SRAM Leakage in Nanometer Technologies

Transactions on High-Performance Embedded Architectures and Compilers III - Lecture Notes in Computer Science ◽

10.1007/978-3-642-19448-1_15 ◽

2011 ◽

pp. 275-299

Author(s):

Maziar Goudarzi ◽

Tohru Ishihara ◽

Hamid Noori

Keyword(s):

Instruction Cache ◽

Leakage Reduction

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Design Methodology and Software Tool for Estimation of Multi-level Instruction Cache Memory Miss Rate

Lecture Notes in Computer Science - Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation ◽

10.1007/978-3-540-74442-9_49 ◽

2007 ◽

pp. 505-515

Author(s):

N. Kroupis ◽

D. Soudris

Keyword(s):

Design Methodology ◽

Software Tool ◽

Cache Memory ◽

Instruction Cache ◽

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Power Reduction of a Set-Associative Instruction Cache Using a Dynamic Early Tag Lookup

10.23919/date51398.2021.9474191 ◽

2021 ◽

Author(s):

Chun-Chang Yu ◽

Yu Hen Hu ◽

Yi-Chang Lu ◽

Charlie Chung-Ping Chen

Keyword(s):

Power Reduction ◽

Instruction Cache

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Performance Estimation of Embedded Software with Instruction Cache Modeling

Readings in Hardware/Software Co-Design ◽

10.1016/b978-155860702-6/50015-6 ◽

2002 ◽

pp. 167-178 ◽

Author(s):

YAU-TSUN STEVEN LI ◽

SHARAD MALIK ◽

ANDREW WOLFE

Keyword(s):

Embedded Software ◽

Performance Estimation ◽

Instruction Cache ◽

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