IMPROVEMENT OF POWER EFFICIENCY AND OUTPUT VOLTAGE RIPPLE OF EMBEDDED DC–DC CONVERTERS WITH THREE STEP DOWN RATIOS

2012 ◽  
Vol 21 (01) ◽  
pp. 1250007 ◽  
Author(s):  
KAUSHIK BHATTACHARYYA ◽  
P. V. RATNA KUMAR ◽  
PRADIP MANDAL
Keyword(s):  
Power Efficiency ◽  
Output Voltage ◽  
Cmos Process ◽  
Switched Capacitor ◽  
Switching Scheme ◽  
Time Interleaving ◽  
Regulation Scheme ◽  
Voltage Ripple ◽  
Switched Capacitor Converter ◽  
On Chip

In this paper three embedded switched capacitor based DC–DC converters targeting Vdd/2, 2Vdd/3, and Vdd/3 output voltages have been designed with improved power efficiency and output voltage ripple. The performance of each of the converter is improved by nonoverlapped rotational time interleaving (NRTI) switching scheme. Current regulation scheme is included with each of the above NRTI switched capacitor converter to achieve better load and line regulation. The proposed converters are designed and simulated in a 0.18 μm n-well CMOS process with the total flying capacitance of 330 pF and load capacitor of 50 pF. The capacitance values are kept within on-chip implementable range. The maximum power efficiency and the output voltage ripple of the integrated NRTI DC–DC converters targeted for Vdd/2, 2Vdd/3 and Vdd/3 output generation are 71.5% and 5 mV, 69.23% and 13.27 mV and 58.09% and 10.5 mV, respectively.

A HIGH EFFICIENCY ADAPTIVE CURRENT MODE STEP-UP/STEP-DOWN DC–DC CONVERTER WITH FOUR MODES FOR SMOOTH TRANSITION

2014 ◽  
Vol 23 (07) ◽  
pp. 1450097 ◽  
Author(s):  
YANZHAO MA ◽  
SHAOXI WANG ◽  
SHENGBING ZHANG ◽  
XIAOYA FAN
Keyword(s):  
Transient Response ◽  
Output Voltage ◽  
High Efficiency ◽  
Current Mode ◽  
Smooth Transition ◽  
Maximum Efficiency ◽  
Cmos Process ◽  
Voltage Ripple ◽  
Transition Modes ◽  
Step Down

This paper presents a current mode step-up/step-down DC–DC converter with high efficiency, small output voltage ripple, and fast transient response. The control scheme adaptively configures the converter into the proper operation mode. The efficiency is improved by reducing the switching loss, wherein the converter operates like a buck or boost converter, and conduction loss, wherein the average inductor current is reduced in transition modes. The output voltage ripple is significantly reduced by incorporating two constant time transition modes. A fast line transient response is achieved with small overshoot and undershoot voltage. An adaptive substrate selector (ASS) is introduced to dynamically switch the substrate of PMOS power transistors to the highest on-chip voltage. A lossless self-biased current sensor with high-speed and high-accuracy is also achieved. The proposed converter was designed with a standard 0.5 μm CMOS process, and can regulate an output voltage within the input voltage ranged from 2.5 V to 5.5 V. The maximum load current is 600 mA, and the maximum efficiency is 94%. The output voltage ripple is less than 15 mV in all operation modes.

On-Chip Power Management DC/DC Switched-Capacitor Converter

2016 ◽  
pp. 179-212
Author(s):  
Gael Pillonnet ◽  
Thomas Souvignet ◽  
Bruno Allard
Keyword(s):  
Power Management ◽  
Switched Capacitor ◽  
Switched Capacitor Converter ◽  
On Chip
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