A Memetic Algorithm-Based Design Space Exploration for Datapath Resource Allocation During High-Level Synthesis

2019 ◽  
Vol 29 (01) ◽  
pp. 2050001
Author(s):  
Shathanaa Rajmohan ◽  
N. Ramasubramanian

System designers have started adopting high-level synthesis (HLS) for architectural design because of the higher levels of abstraction offered. The HLS tools provide multiple design choices with tradeoff among different design parameters. Design Space Exploration (DSE) involves optimizing the synthesis options to achieve best tradeoffs among the metrics of interest. With the aim of exploring the design space in a feasible amount of time, we present a novel automated DSE approach. In particular, meeting the constraints presented by different parameters of interest is modeled as a multi-objective problem and solved using Memetic algorithm. The effectiveness of different variations of the Memetic algorithm in solving the DSE problem is studied and a Firefly algorithm-based solution is proposed with a novel probabilistic local search mechanism. The proposed approach is compared with existing solutions and the results prove that the proposed approach outperforms both existing solutions and other variations of Memetic algorithms in terms of convergence time and quality of results. In addition to that, a case study has been included to demonstrate the applicability of the approach. Results show that the proposed approach achieves a 33% improvement in cost, [Formula: see text] improvement in speed and [Formula: see text] improvement in hypervolume.

VLSI Design ◽  
1997 ◽  
Vol 5 (2) ◽  
pp. 211-221
Author(s):  
Fur-Shing Tsai ◽  
Yu-Chin Hsu

This paper presents the design methodology used in PSS1, a high level synthesis system designed for computation dominated applications. It includes a behavior synthesizer and an area optimizer. Based on a pre-defined architecture, the behavior synthesizer translates a description into a number of designs with different delays and hardware costs. Based on a two-level layout model, the area optimizer fine-tunes the physical design using the information feedback from the layout tools. All the tools are linked by an X-window interface in which users can traverse among different tools and interactively change the design parameters. The output is linked to Lager system [7], a silicon assembler. The layout model allows a designer to interactively merge/split modules, change the shape of modules, and define the pin positions of modules. Experiments show that a considerable area improvement has been achieved using this methodology.


Author(s):  
Lorenzo Ferretti ◽  
Jihye Kwon ◽  
Giovanni Ansaloni ◽  
Giuseppe Di Guglielmo ◽  
Luca P. Carloni ◽  
...  

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