Applications of Multi-Objective Optimization to Industrial Processes: A Literature Review

Industrial processes provide several of the products and services required for society. However, each industry faces different challenges from different perspectives, all of which must be reconciled to obtain profitable, productive, controllable, safe and sustainable processes. In this context, multi-objective optimization has become a powerful tool to aid the decision-making mechanism in the synthesis, design, operation and control of such processes. The solution to the mathematical models provides the necessary tools to asses the system performance in terms of different metrics and evaluate the trade-offs between the objectives in conflict. The number of applications of multi- objective optimization in industrial processes is ample and each application has its own challenges. In the present literature review, a broad panorama of the applications in multi-objective optimization is presented, including future perspectives and open questions that still need to be addressed.

E-Government Information Systems (IS) Project Failure in Developing Countries: Lessons from the Literature

E-government information systems (IS) projects experience numerous challenges that can lead to total or partial failure. The project failure factors have been identified and studied by numerous researchers, but the root causes of such failures are not well-articulated. In this study, literature on e-government IS project failures in developing-world contexts is reviewed through the application of qualitative meta-synthesis, design–reality gap analysis, and root cause analysis. In the process, 18 causal factors and 181 root causes are identified as responsible for e-government IS project failures. The most prevalent of the 18 causal factors are found to be inadequate system requirements engineering (with 22 root causes), inadequate project management (19 root causes), and missing or incomplete features (16 root causes). These findings can be of use to future researchers, policymakers, and practitioners seeking to identify methods of avoiding e-government IS failures, particularly in developing-world contexts.

A Dual-Wideband Balanced Bandpass Filter Based on Branch-Line Structure With Controllable Common-Mode Suppression

In this paper, a novel dual-wideband balanced bandpass filter (BPF) based on branch-line structure is proposed. For analysis, the equivalent circuits of differential-mode (DM) and common-mode (CM) of the filter are built based on the even- and odd-mode method. With a proper synthesis design of DM bisection, dual passbands with a multi-order filtering response can be obtained. Additionally, three open-circuited stubs are centrally loaded on the CM bisection and six controllable transmission zeros are therefore generated. Thus, two stopbands are formed and then a favorable CM suppression within DM passbands is obtained. For demonstration, a third-order dual-wideband balanced BPF is designed with two passbands operating at 2.54 and 4.62 GHz. Good agreement between the simulated results and measured results is obtained, which verifies the validity of the proposed design method.

HOBFLOPS for CNNs: Hardware Optimized Bitslice-Parallel Floating-Point Operations for Convolutional Neural Networks

Low-precision floating-point (FP) can be highly effective for convolutional neural network (CNN) inference. Custom low-precision FP can be implemented in field programmable gate array (FPGA) and application-specific integrated circuit (ASIC) accelerators, but existing microprocessors do not generally support fast, custom precision FP. We propose hardware optimized bitslice-parallel floating-point operators (HOBFLOPS), a generator of efficient custom precision emulated bitslice-parallel software(C/C++) FP arithmetic. We generate custom-precision FP routines, optimized using a hardware synthesis design flow, to create circuits. We provide standard cell libraries matching the bitwise operations on the target microprocessor architecture and a code generator to translate the hardware circuits to bitslice software equivalents. We exploit bitslice parallelism to create a novel, very wide (32—512 element) vectorized CNN convolution for inference. On Arm and Intel processors, the multiply-accumulate (MAC) performance in CNN convolution of HOBFLOPS, Flexfloat, and Berkeley’s SoftFP are compared. HOBFLOPS outperforms Flexfloat by up to 10× on Intel AVX512. HOBFLOPS offers arbitrary-precision FP with custom range and precision, e . g ., HOBFLOPS9, which outperforms Flexfloat 9-bit on Arm Neon by 7×. HOBFLOPS allows researchers to prototype different levels of custom FP precision in the arithmetic of software CNN ac celerators. Furthermore, HOBFLOPS fast custom-precision FP CNNs may be valuable in cases where memory bandwidth is limited.