Alleviation of Data Timing Channels in Normalized/Subnormal Floating Point Multiplier

Floating point (FP) multiplication goes down in the scientific application when it sustains the subnormal inputs either in the implementation of software or hardware. Any high-level language executes the FP instructions in the graphics processing unit (GPU) and floating-point unit (FPU) for supporting the normalized numbers alone. In FP multiplication, execution times for normalized and subnormal numbers are not equal. Execution time variations create unintentional delay and data timing channels (DTCs). A circuit is proposed for floating-point multiplication to minimize the unintentional delay for the holistic support of subnormal numbers. In this proposed four-path FP multiplication, the circuit produces the four types of output in four paths having different delays for all cases of input combination. These four paths are establishing the DTCs. A maximum delay path is taken into account to combine and equalize the four paths into a single output path. Two levels of the control circuit combine the four paths to a single path for reducing the DTC effect. To evaluate the performance after path equalization, the proposed FP multiplier is implemented in Stratix-IV and Cyclone-IV FPGAs with a delay of 57.25 and 82.82 ns, respectively. Here, eight pipeline stages reduce the delay and improve the operating speed of the entire circuit. Stage delay and operating speed for this FP multiplier in both FPGA implementations are 12.44 and 16.86[Formula: see text]ns, and 153.19 and 116.78[Formula: see text]MHz, respectively.