ALGORITHM FOR WIRE SIZING OF POWER AND GROUND NETWORKS IN VLSI DESIGNS

Distributing power and ground to the elements present in a VLSI chip is a very crucial task in the design process. Power networks carry substantial currents and wires carrying them have to be carefully designed to avoid damage caused by electromigration and should not experience significant voltage drops. This paper presents a fast and efficient method for sizing power/ground networks. No restrictions on network topology or the number of supplying pads are imposed. Wire widths are calculated such that the weighted area of wire segments is minimized while electromigration and voltage drops constraints are fulfilled. The algorithm proposed here runs 50% faster for unrestricted topologies than the best methods reported in literature for tree type networks.