Design and Implementation of Power-Efficient FSM based UART

The remarkable innovations in technology are driven mainly by the high-speed data communication requirements of the modern generation. The Universal Asynchronous Receiver Transmitter (UART) is one of the most sought-after communication protocols. This work mainly focuses on implementing and analysing the UART for data communication. The Finite State Machine (FSM) implements the baud rate generator, transmitter, and receiver modules. Cadence NCSIM was utilized for simulation, and Cadence RTL Compiler was used during synthesis using the 45 nm and 90 nm General Process Design Kit (GPDK) library files. The baud rate of 9600 bps and 50 MHz clock frequency was used to design UART. The increased speed and complexity of the VLSI chip designs has resulted in a significant increase in power consumption. The comparative analysis of power and delay for different clock periods shows an improvement in the total power and the Power Delay Product (PDP) with increasing clock periods. Better results were observed using 45 nm in comparison to the 90 nm library.

Towards on-chip real-time classification of extra-cellular neural recordings

On-line classification of neural recordings can be extremely useful in brain-machine interface, prosthetic applications or therapeutic intervention. In this work we present a feasibility study for developing compact low-power VLSI systems able to classify neural recordings in real-time, using spike-based neuromorphic circuits. We developed a framework for classifying extra-cellular recordings made in rat auditory cortex in response to different auditory stimuli and porting the classification algorithm onto a spiking multi-neuron VLSI chip with programmable synaptic weights. We present recording methods and software classification algorithms; we demonstrate real-time classification in hardware and quantify the system performance; finally, we identify the potential sources of problems in developing such types of systems and propose strategies for overcoming them.

A New Approach for a Unified Architecture for Type IV DCT/DST with an Efficient Incorporation of Obfuscation Technique

This paper aims at solving one challenging problem in designing VLSI chips, namely, the security of the hardware, by presenting a new design approach that incorporates the obfuscation technique in the VLSI implementation of some important DSP algorithms. The proposed method introduces a new approach in obtaining a unified VLSI architecture for computing type IV discrete cosine transform (DCT-IV) and type IV discrete sine transform (DST-IV), with an efficient integration of the obfuscation technique, while maintaining low overheads. The algorithms for these two transforms were restructured in such a way that their structures are fairly similar, and thus they can be implemented on the same VLSI chip and on the same hardware with very few modifications, with the latter being attributed to the pre-processing and post-processing stages. The design proposed uses the regular and modular structures, which are named quasi-correlation, and the architecture is inspired by the paradigm of the systolic array architecture. Thus, the introduced design benefits the security, for the hardware, and also the advantages introduced by the use of the regular and modular structures. A very efficient, unified VLSI architecture for type IV DCT/DST can be obtained, which allows the computation of the two algorithms on the same hardware, allowing an efficient incorporation of the obfuscation technique with very low overheads, and it can be very efficiently implemented, offering high-speed performances and low hardware complexity, with the latter being attributed to the efficient use of the hardware resources for the computation of these two algorithms.

Low Power Circuit Design for Footed Quasi Resistance Scheme In 45NM VLSI Technology

Low power has arisen as a chief topic in these days and hardware enterprises. Power dissipation has become a significant thought as execution and zone of VLSI Chip plan. In this paper, a design of low power for footed quasi resistance scheme in 45nanometer VLSI technology, using appropriate standard digital gates with 45nm technology, considering footed quasi resistance technique for nanoscales is introduced. Transition of logic 1 and 0 is the main problem in the cascading circuits, this problem can solved by employing a basic inverter called as Domino logic at output.Due to the precharge propagation the power dissipation is observed in domino logic, this will be resolved using PDB (Pseudo Dynamic Buffer) model. With the help of PDB nearly 67% of power saved. Even though PDB is succeeded in precharge propagation, it fails in logic transition, this may results erroneous output during cascading. With contracting technology, power utilization can decreased and over all power of the executives on chip are the critical difficulties below 100nm because of expanded intricacy. In this paper execution of low power circuit scheme for footed quasi resistance plot in 45nm VLSI technology. In this paper we will actualize and recreate low power circuit scheme for footed quasi resistance plot in 45nm VLSI technology.

DECODING TECHNIQUE FOR LOW POWER DESIGN IN XILINX

This research paper is a survey of the current status of research and practice in various disciplines of low power VLSI developments. The paper briefly discusses the rationale of the contemporary, and concentrates on low power design, it presents the metrics and techniques that are used to access the merits of the assorted proposed for the improved energy efficiency. Power dissipation [1], [5] has become an important consideration in terms of performance and scope for VLSI chip design. The research paper describes the decoding strategies, methodology, and techniques for low power system design. Here also we have proposed the decoding technique and compared with silent coding to scale back the transition state and conserved the power which is additionally described during this research. KEYWORDS—Power minimization, decoding technique, silent coding.

Evaluating the Reliability Testing Acceleration Factor Based on VLSI Chip Infrared Image Analysis

A new approach for evaluating the acceleration factor of forced reliability tests of very large scale integrated circuits (VLSI) is presented. The approach is based on subjecting the VLSI chip to an infrared image analysis. Currently, the VLSI reliability testing acceleration factor is evaluated based on the Arrhenius law, according to which this factor depends on the chip temperature. The chip temperature, in turn, is represented by the sum of the chip package temperature and the product of the maximum dissipated power and the chip-to-package thermal resistance. The drawback of the existing method is that the calculation is carried out for only a single chip temperature value that was obtained analytically. But the VLSI is a complex system, and it is not correct to judge about the testing acceleration factor proceeding from a single chip temperature value. It is proposed to calculate the VLSI reliability testing acceleration factor based on the temperatures at many points on the VLSI chip surface. This will make it possible to take into account the test sequence influence on the temperature distribution over the chip surface, thereby helping select the test sequences so that to obtain the maximal and uniform chip heating. Owing to the proposed method, it becomes possible to evaluate the testing acceleration factor more accurately and also to potentially increase it by choosing the test sequence. A more accurate evaluation of the acceleration factor allows the reliability tests reliability to be improved. The proposed method for evaluating the acceleration factor was validated experimentally. The workplace is described, the calculations of the reliability testing acceleration factors using two approaches are carried out, and their comparison is given.

SneakySnake: a fast and accurate universal genome pre-alignment filter for CPUs, GPUs and FPGAs

Motivation We introduce SneakySnake, a highly parallel and highly accurate pre-alignment filter that remarkably reduces the need for computationally costly sequence alignment. The key idea of SneakySnake is to reduce the approximate string matching (ASM) problem to the single net routing (SNR) problem in VLSI chip layout. In the SNR problem, we are interested in finding the optimal path that connects two terminals with the least routing cost on a special grid layout that contains obstacles. The SneakySnake algorithm quickly solves the SNR problem and uses the found optimal path to decide whether or not performing sequence alignment is necessary. Reducing the ASM problem into SNR also makes SneakySnake efficient to implement on CPUs, GPUs and FPGAs. Results SneakySnake significantly improves the accuracy of pre-alignment filtering by up to four orders of magnitude compared to the state-of-the-art pre-alignment filters, Shouji, GateKeeper and SHD. For short sequences, SneakySnake accelerates Edlib (state-of-the-art implementation of Myers’s bit-vector algorithm) and Parasail (state-of-the-art sequence aligner with a configurable scoring function), by up to 37.7× and 43.9× (>12× on average), respectively, with its CPU implementation, and by up to 413× and 689× (>400× on average), respectively, with FPGA and GPU acceleration. For long sequences, the CPU implementation of SneakySnake accelerates Parasail and KSW2 (sequence aligner of minimap2) by up to 979× (276.9× on average) and 91.7× (31.7× on average), respectively. As SneakySnake does not replace sequence alignment, users can still obtain all capabilities (e.g. configurable scoring functions) of the aligner of their choice, unlike existing acceleration efforts that sacrifice some aligner capabilities. Availabilityand implementation https://github.com/CMU-SAFARI/SneakySnake. Supplementary information Supplementary data are available at Bioinformatics online.

DESIGN OF FAULT-TOLERANT CHIP INTERFACES

The article discusses the process of designing the interface of fault-tolerant chips. A redundant internal interface is designed for integrating system components on chips into a single information exchange system. The paper describes the interface for the four-channel construction of the VLSI chip of the BMC SNK. Special attention is paid to the description of interface signals.

Multi-Core Eight Bit Ternary Content-Addressable Memory Design Based Image Learning System

In this research work, the image is learned to find features to make use of during its analysis and a genetic apices based low power Ternary Content-Addressable Memory (TCAM) is designed to implement the proposed image learning system. A technique called Content Matching Search Register is proposed in this work to perform the image learning operations in proposed TCAM architecture. This paper proposes an ImOFF algorithm for image analysis. The focus of this multi-core TCAM (MC-TCAM) is to make fast computations and search based designs. The focus application of this research work is in the design of low power On-board Embedded-VLSI chip to perform image analysis. Proposed multi-core eight bit Ternary TCAM (MCEB-TCAM) is analyzed using IC design tools in 90nm technology, using Verilog hardware description language and usage of Cadence for layout generation and parasitic extraction of the circuit components.