A SIMULATED ANNEALING ALGORITHM FOR SYSTEM-ON-CHIP TEST SCHEDULING WITH, POWER AND PRECEDENCE CONSTRAINTS

2006 ◽  
Vol 06 (04) ◽  
pp. 511-530 ◽  
Author(s):  
HAIDAR M. HARMANANI ◽  
HASSAN A. SALAMY
Keyword(s):  
Simulated Annealing ◽  
Simulated Annealing Algorithm ◽  
System On Chip ◽  
Precedence Constraints ◽  
Test Scheduling ◽  
Optimal Test ◽  
Power Constraints ◽  
Soc Test ◽  
On Chip ◽  
Minimum System

This paper presents an efficient method to determine minimum system-on-chip (SOC) test schedules with precedence and power constraints based on simulated annealing. The problem is solved using a partitioned testing scheme with run to completion that minimizes the number of idle test slots. The method can handle SOC test scheduling with and without power constraints in addition to precedence constraints that preserve desirable orderings among tests. We present experimental results for various SOC examples that demonstrate the effectiveness of the method. The method achieved optimal test schedules in all attempted cases in a short CPU time.

scholarly journals An Improved SoC Test Scheduling Method Based on Simulated Annealing Algorithm

2017 ◽  
Vol 806 ◽  
pp. 012011
Author(s):  
Jingjing Zheng ◽  
Zhihang Shen ◽  
Huaien Gao ◽  
Bianna Chen ◽  
Weida Zheng ◽  
...  
Keyword(s):  
Simulated Annealing ◽  
Simulated Annealing Algorithm ◽  
Test Scheduling ◽  
Soc Test ◽  
Scheduling Method ◽  
Annealing Algorithm

A Strength Pareto Evolutionary Algorithm for Optimizing System-On-Chip Test Schedules

2018 ◽  
Vol 17 (02) ◽  
pp. 1850010
Author(s):  
Wissam Marrouche ◽  
Rana Farah ◽  
Haidar M. Harmanani
Keyword(s):  
Evolutionary Algorithm ◽  
System On Chip ◽  
Test Scheduling ◽  
Scheduling Problem ◽  
Single Chip ◽  
Simultaneous Test ◽  
Soc Test ◽  
Strength Pareto Evolutionary Algorithm ◽  
Tightly Coupled ◽  
On Chip

System-on-chip (SOC) has become a mainstream design practice that integrates intellectual property cores on a single chip. The SOC test scheduling problem maximizes the simultaneous test of all cores by determining the order in which various cores are tested. The problem is tightly coupled with the test access mechanism (TAM) bandwidth and wrapper design. This paper presents a strength Pareto evolutionary algorithm for the SOC test scheduling problem with the objective of minimizing the power-constrained test application time, wrapper design and TAM assignment in flat and hierarchical core-based systems. We demonstrate the effectiveness of the method using the ITC’02 benchmarks.

Test scheduling of System-on-Chip using Dragonfly and Ant Lion optimization algorithms

2020 ◽  
pp. 1-13
Author(s):  
Gokul Chandrasekaran ◽  
P.R. Karthikeyan ◽  
Neelam Sanjeev Kumar ◽  
Vanchinathan Kumarasamy
Keyword(s):  
Ant Colony Optimization ◽  
Artificial Bee Colony ◽  
Optimization Algorithms ◽  
System On Chip ◽  
Test Time ◽  
Test Scheduling ◽  
Bee Colony ◽  
Ant Lion Optimization ◽  
Ant Lion ◽  
On Chip

Test scheduling of System-on-Chip (SoC) is a major problem solved by various optimization techniques to minimize the cost and testing time. In this paper, we propose the application of Dragonfly and Ant Lion Optimization algorithms to minimize the test cost and test time of SoC. The swarm behavior of dragonfly and hunting behavior of Ant Lion optimization methods are used to optimize the scheduling time in the benchmark circuits. The proposed algorithms are tested on p22810 and d695 ITC’02 SoC benchmark circuits. The results of the proposed algorithms are compared with other algorithms like Ant Colony Optimization, Modified Ant Colony Optimization, Artificial Bee Colony, Modified Artificial Bee Colony, Firefly, Modified Firefly, and BAT algorithms to highlight the benefits of test time minimization. It is observed that the test time obtained for Dragonfly and Ant Lion optimization algorithms is 0.013188 Sec for D695, 0.013515 Sec for P22810, and 0.013432 Sec for D695, 0.013711 Sec for P22810 respectively with TAM Width of 64, which is less as compared to the other well-known optimization algorithms.

A Novel System on Chip (SoC) Test Solution

2008 ◽  
Author(s):  
Michael Higgins ◽  
Ciaran MacNamee ◽  
Brendan Mullane
Keyword(s):  
System On Chip ◽  
Test Solution ◽  
Soc Test ◽  
On Chip

Minimization of test time in system on chip using artificial intelligence-based test scheduling techniques

2019 ◽  
Vol 32 (9) ◽  
pp. 5303-5312 ◽  
Author(s):  
Gokul Chandrasekaran ◽  
Sakthivel Periyasamy ◽  
Karthikeyan Panjappagounder Rajamanickam
Keyword(s):  
Artificial Intelligence ◽  
System On Chip ◽  
Test Time ◽  
Test Scheduling ◽  
On Chip
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