Proceedings. 21st VLSI Test Symposium, 2003.
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61

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15

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0769519245

Latest Documents Most Cited Documents Contributed Authors Related Sources Related Keywords

Keynote Address

Proceedings. 21st VLSI Test Symposium, 2003. ◽

10.1109/vtest.2003.1197623 ◽

2005 ◽

Author(s):

J. Fields

Keyword(s):

Keynote Address

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Building yield into systems-on chips for nanometer technologies

Proceedings. 21st VLSI Test Symposium, 2003. ◽

10.1109/vtest.2003.1197624 ◽

2005 ◽

Author(s):

P. Magarshack

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An analog checker with dynamically adjustable error threshold for fully differential circuits

Proceedings. 21st VLSI Test Symposium, 2003. ◽

10.1109/vtest.2003.1197653 ◽

2003 ◽

Cited By ~ 10

Author(s):

H.G. Stratigopoulos ◽

Y. Makris

Keyword(s):

Error Threshold ◽

Fully Differential ◽

Differential Circuits

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A test interface for built-in test of non-isolated scanned cores

Proceedings. 21st VLSI Test Symposium, 2003. ◽

10.1109/vtest.2003.1197677 ◽

2003 ◽

Author(s):

I. Porneranz ◽

S.M. Reddy ◽

Y. Zorian

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BIST-aided scan test - a new method for test cost reduction

Proceedings. 21st VLSI Test Symposium, 2003. ◽

10.1109/vtest.2003.1197675 ◽

2003 ◽

Cited By ~ 37

Author(s):

T. Hiraide ◽

Kwame Osei Boateng ◽

H. Konishi ◽

K. Itaya ◽

M. Emori ◽

...

Keyword(s):

Cost Reduction ◽

New Method ◽

Test Cost ◽

Scan Test ◽

Test Cost Reduction

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Test data compression and test time reduction of longest-path-per-gate tests based on Illinois scan architecture

Proceedings. 21st VLSI Test Symposium, 2003. ◽

10.1109/vtest.2003.1197628 ◽

2003 ◽

Cited By ~ 7

Author(s):

M. Sharma ◽

J.H. Patel ◽

J. Rearick

Keyword(s):

Data Compression ◽

Test Data ◽

Test Time ◽

Test Data Compression ◽

Test Time Reduction ◽

Longest Path ◽

Time Reduction

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Deterministic test vector decompression in software using linear operations [SOC testing]

Proceedings. 21st VLSI Test Symposium, 2003. ◽

10.1109/vtest.2003.1197655 ◽

2003 ◽

Cited By ~ 8

Author(s):

K.J. Balakrishnan ◽

N.A. Touba

Keyword(s):

Test Vector ◽

Soc Testing

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Test and diagnosis of word-oriented multiport memories

Proceedings. 21st VLSI Test Symposium, 2003. ◽

10.1109/vtest.2003.1197658 ◽

2003 ◽

Cited By ~ 5

Author(s):

Chih-Wea Wang ◽

Kuo-Liang Cheng ◽

Chih-Tsun Huang ◽

Cheng-Wen Wu

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Fault testing for reversible circuits

Proceedings. 21st VLSI Test Symposium, 2003. ◽

10.1109/vtest.2003.1197682 ◽

2003 ◽

Cited By ~ 26

Author(s):

K.N. Patel ◽

J.P. Hayes ◽

I.L. Markov

Keyword(s):

Fault Testing ◽

Reversible Circuits

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Effectiveness of I-V testing in comparison to IDDq tests [IC testing]

Proceedings. 21st VLSI Test Symposium, 2003. ◽

10.1109/vtest.2003.1197632 ◽

2003 ◽

Cited By ~ 2

Author(s):

T.J. Vogels

Keyword(s):

Ic Testing

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