Clustered voltage scaling technique for low-power design

1995 ◽  
Author(s):  
Kimiyoshi Usami ◽  
Mark Horowitz
Keyword(s):  
Low Power ◽  
Low Power Design ◽  
Voltage Scaling ◽  
Scaling Technique

scholarly journals Variations-aware low-power design with voltage scaling

2005 ◽  
Author(s):  
Navid Azizi ◽  
Muhammad M. Khellah ◽  
Vivek De ◽  
Farid N. Najm
Keyword(s):  
Low Power ◽  
Low Power Design ◽  
Voltage Scaling

scholarly journals AN OPTIMIZATION-BASED MULTIPLE-VOLTAGE SCALING TECHNIQUE FOR LOW-POWER CMOS DIGITAL DESIGN

2002 ◽  
Vol 11 (04) ◽  
pp. 365-375 ◽  
Author(s):  
YI-JONG YEH ◽  
SY-YEN KUO
Keyword(s):  
Low Power ◽  
Voltage Scaling ◽  
Path Selection ◽  
Digital Design ◽  
Selection Algorithm ◽  
Scaling Technique ◽  
Low Power Cmos ◽  
Optimal Values ◽  
Supply Voltages ◽  
Multiple Supply Voltages

In this paper, we propose a voltage scaling technique with multiple supply voltages for low-power designs. We adopt the path sensitization technique and release the clustering constraint used by the previous works. Our technique first operates the gates with the lowest feasible supply voltages and then uses an existing path selection algorithm for optimization. Experiments are conducted on all ISCAS85 benchmarks and the results show that significant power can be further reduced by our technique in comparison with the previous works. Furthermore, the results generated by our technique are close to the optimal values.

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