2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)

MixNet: An Energy-Scalable and Computationally Lightweight Deep Learning Accelerator

2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) ◽

10.1109/islped.2019.8824978 ◽

2019 ◽

Author(s):

Sangwoo Jung ◽

Seungsik Moon ◽

Youngjoo Lee ◽

Jaeha Kung

Keyword(s):

Deep Learning

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Energy-Autonomous MCU Operating in sub-VT Regime with Tightly-Integrated Energy-Harvester : A SoC for IoT smart nodes containing a MCU with minimum-energy point of 2.9pJ/cycle and a harvester with output power range from sub-µW to 4.32mW

2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) ◽

10.1109/islped.2019.8824829 ◽

2019 ◽

Cited By ~ 1

Author(s):

J. Deng ◽

J-L Nagel ◽

L. Zahnd ◽

M. Pons ◽

D. Ruffieux ◽

...

Keyword(s):

Output Power ◽

Energy Harvester ◽

Minimum Energy ◽

Energy Point ◽

Minimum Energy Point

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A 65nm switched source line sub-threshold ROM using data encoding, with 0.3V Vmin and 47fJ/b access energy

2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) ◽

10.1109/islped.2019.8824967 ◽

2019 ◽

Cited By ~ 1

Author(s):

Supreet Jeloka ◽

Pranay Prabhat ◽

Graham Knight ◽

James Myers

Keyword(s):

Data Encoding ◽

Source Line ◽

Using Data

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RAPID: A ReRAM Processing in-Memory Architecture for DNA Sequence Alignment

2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) ◽

10.1109/islped.2019.8824830 ◽

2019 ◽

Cited By ~ 2

Author(s):

Saransh Gupta ◽

Mohsen Imani ◽

Behnam Khaleghi ◽

Venkatesh Kumar ◽

Tajana Rosing

Keyword(s):

Dna Sequence ◽

Sequence Alignment ◽

Memory Architecture ◽

Dna Sequence Alignment

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A Low-Power and Low-Noise 20:1 Serializer with Two Calibration Loops in 55-nm CMOS

2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) ◽

10.1109/islped.2019.8824879 ◽

2019 ◽

Cited By ~ 1

Author(s):

Yong-Un Jeong ◽

Joo-Hyung Chae ◽

Sungphil Choi ◽

Jaekwang Yun ◽

Shin-Hyun Jeong ◽

...

Keyword(s):

Low Power ◽

Low Noise

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A Logic Compatible 4T Dual Embedded DRAM Array for In-Memory Computation of Deep Neural Networks

2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) ◽

10.1109/islped.2019.8824826 ◽

2019 ◽

Cited By ~ 5

Author(s):

Taegeun Yoo ◽

Hyunjoon Kim ◽

Qian Chen ◽

Tony Tae-Hyoung Kim ◽

Bongjin Kim

Keyword(s):

Neural Networks ◽

Deep Neural Networks

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Muffin: Minimally-Buffered Zero-Delay Power-Gating Technique in On-Chip Routers

2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) ◽

10.1109/islped.2019.8824806 ◽

2019 ◽

Cited By ~ 1

Author(s):

Hossein Farrokhbakht ◽

Hadi Mardani Kamali ◽

Natalie Enright Jerger

Keyword(s):

Power Gating ◽

On Chip

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Exploring the Relation between Monolithic 3D L1 GPU Cache Capacity and Warp Scheduling Efficiency

2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) ◽

10.1109/islped.2019.8824947 ◽

2019 ◽

Author(s):

Cong Thuan Do ◽

Young-Ho Gong ◽

Cheol Hong Kim ◽

Seon Wook Kim ◽

Sung Woo Chung

Keyword(s):

Cache Capacity

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SECO: A Scalable Accuracy Approximate Exponential Function Via Cross-Layer Optimization

2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) ◽

10.1109/islped.2019.8824959 ◽

2019 ◽

Cited By ~ 5

Author(s):

Di Wu ◽

Tianen Chen ◽

Chienfu Chen ◽

Oghenefego Ahia ◽

Joshua San Miguel ◽

...

Keyword(s):

Exponential Function ◽

Cross Layer ◽

Cross Layer Optimization

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A Low-Energy Inductive Transceiver using Spike-Latency Encoding for Wireless 3D Integration

2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) ◽

10.1109/islped.2019.8824866 ◽

2019 ◽

Author(s):

Benjamin J. Fletcher ◽

Shidhartha Das ◽

Terrence Mak

Keyword(s):

Low Energy ◽

3D Integration ◽

Spike Latency

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2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)
Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

MixNet: An Energy-Scalable and Computationally Lightweight Deep Learning Accelerator

Energy-Autonomous MCU Operating in sub-VT Regime with Tightly-Integrated Energy-Harvester : A SoC for IoT smart nodes containing a MCU with minimum-energy point of 2.9pJ/cycle and a harvester with output power range from sub-µW to 4.32mW

A 65nm switched source line sub-threshold ROM using data encoding, with 0.3V Vmin and 47fJ/b access energy

RAPID: A ReRAM Processing in-Memory Architecture for DNA Sequence Alignment

A Low-Power and Low-Noise 20:1 Serializer with Two Calibration Loops in 55-nm CMOS

A Logic Compatible 4T Dual Embedded DRAM Array for In-Memory Computation of Deep Neural Networks

Muffin: Minimally-Buffered Zero-Delay Power-Gating Technique in On-Chip Routers

Exploring the Relation between Monolithic 3D L1 GPU Cache Capacity and Warp Scheduling Efficiency

SECO: A Scalable Accuracy Approximate Exponential Function Via Cross-Layer Optimization

A Low-Energy Inductive Transceiver using Spike-Latency Encoding for Wireless 3D Integration

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2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)Latest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

MixNet: An Energy-Scalable and Computationally Lightweight Deep Learning Accelerator

Energy-Autonomous MCU Operating in sub-VT Regime with Tightly-Integrated Energy-Harvester : A SoC for IoT smart nodes containing a MCU with minimum-energy point of 2.9pJ/cycle and a harvester with output power range from sub-µW to 4.32mW

A 65nm switched source line sub-threshold ROM using data encoding, with 0.3V Vmin and 47fJ/b access energy

RAPID: A ReRAM Processing in-Memory Architecture for DNA Sequence Alignment

A Low-Power and Low-Noise 20:1 Serializer with Two Calibration Loops in 55-nm CMOS

A Logic Compatible 4T Dual Embedded DRAM Array for In-Memory Computation of Deep Neural Networks

Muffin: Minimally-Buffered Zero-Delay Power-Gating Technique in On-Chip Routers

Exploring the Relation between Monolithic 3D L1 GPU Cache Capacity and Warp Scheduling Efficiency

SECO: A Scalable Accuracy Approximate Exponential Function Via Cross-Layer Optimization

A Low-Energy Inductive Transceiver using Spike-Latency Encoding for Wireless 3D Integration

2019 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)
Latest Publications