Low power 3-D stacking multimedia platform with reconfigurable memory architecture

Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI - GLSVLSI '13 ◽

10.1145/2483028.2483117 ◽

2013 ◽

Author(s):

Po-Han Huang ◽

Huang-Lun Lin ◽

Hsien-Ching Hsieh ◽

Chi-Hung Lin ◽

Shui-An Wen ◽

...

Keyword(s):

Low Power ◽

Memory Architecture ◽

Reconfigurable Memory

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A Low Power Reconfigurable Memory Architecture for Complementary Resistive Switches

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/tcad.2019.2927520 ◽

2020 ◽

Vol 39 (9) ◽

pp. 1806-1819 ◽

Author(s):

Bing Wu ◽

Dan Feng ◽

Wei Tong ◽

Jingning Liu ◽

Chengning Wang ◽

...

Keyword(s):

Low Power ◽

Memory Architecture ◽

Resistive Switches ◽

Reconfigurable Memory

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Embedded Memory Architecture for Low-Power Application Processor

Integrated Circuits and Systems - Embedded Memories for Nano-Scale VLSIs ◽

10.1007/978-0-387-88497-4_2 ◽

2009 ◽

pp. 7-38 ◽

Author(s):

Hoi Jun Yoo ◽

Donghyun Kim

Keyword(s):

Low Power ◽

Memory Architecture ◽

Embedded Memory ◽

Application Processor ◽

Power Application

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Design and analysis of multiple port memory architecture for low power applications

2018 Conference on Signal Processing And Communication Engineering Systems (SPACES) ◽

10.1109/spaces.2018.8316348 ◽

2018 ◽

Author(s):

T. Subhashini ◽

M. Kamaraju ◽

K. Babulu

Keyword(s):

Low Power ◽

Memory Architecture

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Three-dimensional image processing VLSI system with network-on-chip system and reconfigurable memory architecture

IEEE Transactions on Consumer Electronics ◽

10.1109/tce.2011.6018893 ◽

2011 ◽

Vol 57 (3) ◽

pp. 1345-1353 ◽

Author(s):

Yun Yang

Keyword(s):

Image Processing ◽

Three Dimensional ◽

Network On Chip ◽

Memory Architecture ◽

Dimensional Image ◽

Vlsi System ◽

Reconfigurable Memory ◽

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Low power cross-point memory architecture

IEEE Asian Solid-State Circuits Conference 2011 ◽

10.1109/asscc.2011.6123630 ◽

2011 ◽

Author(s):

Bruce Bateman ◽

Chang Siau ◽

Christophe Chevallier

Keyword(s):

Low Power ◽

Memory Architecture ◽

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A Low-Power Packet Memory Architecture with a Latency-Aware Packet Mapping Method

IEICE Transactions on Information and Systems ◽

10.1587/transinf.e96.d.963 ◽

2013 ◽

Vol E96.D (4) ◽

pp. 963-966

Author(s):

Hyuk-Jun LEE ◽

Seung-Chul KIM ◽

Eui-Young CHUNG

Keyword(s):

Low Power ◽

Mapping Method ◽

Memory Architecture

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Challenge of MTJ-based nonvolatile logic-in-memory architecture for ultra low-power and highly dependable VLSI computing

2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) ◽

10.1109/s3s.2015.7333502 ◽

2015 ◽

Author(s):

Takahiro Hanyu ◽

Masanori Natsui ◽

Daisuke Suzuki ◽

Akira Mochizuki ◽

Naoya Onizawa ◽

...

Keyword(s):

Low Power ◽

Memory Architecture ◽

Ultra Low Power

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A Class Project For Low Power Cache Memory Architecture

10.18260/1-2--6 ◽

2020 ◽

Author(s):

Yul Chu

Keyword(s):

Low Power ◽

Cache Memory ◽

Memory Architecture ◽

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Smart Logic-in-Memory Architecture For Ultra-Low Power Large Fan-In Operations

2020 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS) ◽

10.1109/aicas48895.2020.9073870 ◽

2020 ◽

Author(s):

Tommaso Zanotti ◽

Francesco Maria Puglisi ◽

Paolo Pavan

Keyword(s):

Low Power ◽

Memory Architecture ◽

Ultra Low Power

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Design and Analysis of Ultra-Low Power Memory Architecture with MTCMOS Asymmetrical Ground-Gated 7T SRAM Cell

Lecture Notes in Electrical Engineering - Microelectronics, Circuits and Systems ◽

10.1007/978-981-16-1570-2_12 ◽

2021 ◽

pp. 123-133

Author(s):

Vaibhav Neema ◽

Priyanka Parihar ◽

Santosh Kumar Vishvakarma

Keyword(s):

Low Power ◽

Memory Architecture ◽

Ultra Low Power ◽

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