Probabilistic Spike Propagation for Efficient Hardware Implementation of Spiking Neural Networks

Spiking neural networks (SNNs) have gained considerable attention in recent years due to their ability to model temporal event streams, be trained using unsupervised learning rules, and be realized on low-power event-driven hardware. Notwithstanding the intrinsic desirable attributes of SNNs, there is a need to further optimize their computational efficiency to enable their deployment in highly resource-constrained systems. The complexity of evaluating an SNN is strongly correlated to the spiking activity in the network, and can be measured in terms of a fundamental unit of computation, viz. spike propagation along a synapse from a single source neuron to a single target neuron. We propose probabilistic spike propagation, an approach to optimize rate-coded SNNs by interpreting synaptic weights as probabilities, and utilizing these probabilities to regulate spike propagation. The approach results in 2.4–3.69× reduction in spikes propagated, leading to reduced time and energy consumption. We propose Probabilistic Spiking Neural Network Application Processor (P-SNNAP), a specialized SNN accelerator with support for probabilistic spike propagation. Our evaluations across a suite of benchmark SNNs demonstrate that probabilistic spike propagation results in 1.39–2× energy reduction with simultaneous speedups of 1.16–1.62× compared to the traditional model of SNN evaluation.

Erratum: Borejko, T., et al. NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor. Sensors 2020, 20, 1069

The authors wish to make the following erratum to this paper [...]

NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor

A dual-frequency all-in-one Global Navigation Satellite System (GNSS) receiver with a multi-core 32-bit RISC (reduced instruction set computing) application processor was integrated and manufactured as a System-on-Chip (SoC) in a 110 nm CMOS (complementary metal-oxide semiconductor) process. The GNSS RF (radio frequency) front-end with baseband navigation engine is able to receive, simultaneously, Galileo (European Global Satellite Navigation System) E1/E5ab, GPS (US Global Positioning System) L1/L1C/L5, BeiDou (Chinese Navigation Satellite System) B1/B2, GLONASS (GLObal NAvigation Satellite System of Russian Government) L1/L3/L5, QZSS (Quasi-Zenith Satellite System development by the Japanese government) L1/L5 and IRNSS (Indian Regional Navigation Satellite System) L5, as well as all SBAS (Satellite Based Augmentation System) signals. The ability of the GNSS to detect such a broad range of signals allows for high-accuracy positioning. The whole SoC (system-on-chip), which is connected to a small passive antenna, provides precise position, velocity and time or raw GNSS data for hybridization with the IMU (inertial measurement unit) without the need for an external application processor. Additionally, user application can be executed directly in the SoC. It works in the −40 to +105 °C temperature range with a 1.5 V supply. The assembled test-chip takes 100 pins in a QFN (quad-flat no-leads) package and needs only a quartz crystal for the on-chip reference clock driver and optional SAW (surface acoustic wave) filters. The radio performance for both wideband (52 MHz) channels centered at L1/E1 and L5/E5 is NF = 2.3 dB, G = 131 dB, with 121 dBc/Hz of phase noise @ 1 MHz offset from the carrier, consumes 35 mW and occupies a 4.5 mm2 silicon area. The SoC reported in the paper is the first ever dual-frequency single-chip GNSS receiver equipped with a multi-core application microcontroller integrated with embedded flash memory for the user application program.

Computational storage: an efficient and scalable platform for big data and HPC applications

In the era of big data applications, the demand for more sophisticated data centers and high-performance data processing mechanisms is increasing drastically. Data are originally stored in storage systems. To process data, application servers need to fetch them from storage devices, which imposes the cost of moving data to the system. This cost has a direct relation with the distance of processing engines from the data. This is the key motivation for the emergence of distributed processing platforms such as Hadoop, which move process closer to data. Computational storage devices (CSDs) push the “move process to data” paradigm to its ultimate boundaries by deploying embedded processing engines inside storage devices to process data. In this paper, we introduce Catalina, an efficient and flexible computational storage platform, that provides a seamless environment to process data in-place. Catalina is the first CSD equipped with a dedicated application processor running a full-fledged operating system that provides filesystem-level data access for the applications. Thus, a vast spectrum of applications can be ported for running on Catalina CSDs. Due to these unique features, to the best of our knowledge, Catalina CSD is the only in-storage processing platform that can be seamlessly deployed in clusters to run distributed applications such as Hadoop MapReduce and HPC applications in-place without any modifications on the underlying distributed processing framework. For the proof of concept, we build a fully functional Catalina prototype and a CSD-equipped platform using 16 Catalina CSDs to run Intel HiBench Hadoop and HPC benchmarks to investigate the benefits of deploying Catalina CSDs in the distributed processing environments. The experimental results show up to 2.2× improvement in performance and 4.3× reduction in energy consumption, respectively, for running Hadoop MapReduce benchmarks. Additionally, thanks to the Neon SIMD engines, the performance and energy efficiency of DFT algorithms are improved up to 5.4× and 8.9×, respectively.

Packaging Challenges of Thin High Bandwidth POP

Components for Smartphone has been the biggest driving force of IC industry for years, and one of the most important IC is application processor (AP). AP needs to work with low power double data rate (LPDDR), the mobile DRAM together for the primary processing of cellular phone and other smart functions. At the beginning, they were packaged separately and then mounted onto printed circuit board (PCB) very close to each other. Nowadays, AP for flagship Smartphone is packaged with a variety of PoP (package on package) structures to shorten the communication distance between AP and LPDDR as well as to save more rooms for battery. High bandwidth package on package (HBW-POP) is the most popular structure among them. As compared to other substrate based PoP, HBW-POP provides the most top side pin count while keeps larger ball pitch for system assembly house to mount LPDDR packaged by fine-pitch ball grid array (FBGA) on top of it. And compared to novel Fan-Out based PoP, HBW-POP has lower cost for AP packaging. In addition, maximum package height of HBW-POP has been shrinking. It is because when LPDDR is mounted onto HBW-POP, the combination is always the tallest chips on the PCB, which determines how slim specific Smartphone can be. HBW-POP consists of 3 parts to encapsulate AP die, and they are top 2-layer substrate, middle molding and bottom 3-layer substrate. Each part has its own coefficient of thermal expansion (CTE) and rigidity, and the warpage performance of HBW-POP is important to align the warpage behavior of LPDDR. The warpage of HBW-POP needs to align with FBGA properly during reflow for good joint, but when HBW-POP becomes thinner, the rigidity of its different parts is changed, which result in different warpage behavior during the reflow. In this paper, we will review the challenges of thin HBW-POP packaging, meanwhile we will explore possible solutions to address each challenge. The study includes the screening of different thickness combination of the 3 parts of HBW-POP, and the optimization of the rigidity and CTE of them. Design of Experiments (DOE) are conducted to find solutions which can meet warpage target, and finally, we present more different tests to prove the reliability of our results.