Optimization of FPGA-based LDPC decoder using high-level synthesis

2018 ◽  
Author(s):  
Geon Choi ◽  
Kyeong-Bin Park ◽  
Ki-Seok Chung
Keyword(s):  
High Level Synthesis ◽  
Ldpc Decoder ◽  
High Level

scholarly journals Implementation of an LDPC decoder for IEEE 802.11n using VivadoTM High-Level Synthesis

2021 ◽  
Vol 8 ◽  
pp. 1-4
Author(s):  
Ernest Scheiber ◽  
Guido H. Bruck ◽  
Peter Jung
Keyword(s):  
Forward Error Correction ◽  
Implementation Process ◽  
Research Topic ◽  
High Level Synthesis ◽  
Ldpc Decoder ◽  
The Past ◽  
High Level ◽  
Forward Error ◽  
Hardware Designs ◽  
High Processing

The increasing complexity of hardware designs calls for design methodolgies that use more abstract design entries and increased automation of the implementation process. Highlevel synthesis (HLS) has been a research topic for the past 20 years, and current tools, such as Xilinx VivadoTM HLS promise to bring HLS to widespread use. In this paper we use Xilinx VivadoTMHLS to design an LDPC decoder for 802.11n. Forward error correction decoders are typically implemented in hardware due to the high processing requirements and therefore an LDPC decoder is an appropriate example to demonstrate the power of high-level synthesis

Floorplan-Aware High-Level Synthesis for Generalized Distributed-Register Architectures

2009 ◽  
Vol E92-A (12) ◽  
pp. 3169-3179 ◽  
Author(s):  
Akira OHCHI ◽  
Nozomu TOGAWA ◽  
Masao YANAGISAWA ◽  
Tatsuo OHTSUKI
Keyword(s):  
High Level Synthesis ◽  
High Level

Exact and Practical Modulo Scheduling for High-Level Synthesis

2019 ◽  
Vol 12 (2) ◽  
pp. 1-26 ◽  
Author(s):  
Julian Oppermann ◽  
Melanie Reuter-Oppermann ◽  
Lukas Sommer ◽  
Andreas Koch ◽  
Oliver Sinnen
Keyword(s):  
High Level Synthesis ◽  
Modulo Scheduling ◽  
High Level
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